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Sorin A. Huss: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Abdulhadi Shoufan, Ralf Laue, Sorin A. Huss
    High-Flexibility Rekeying Processor for Key Management in Secure Multicast. [Citation Graph (0, 0)][DBLP]
    AINA Workshops (1), 2007, pp:822-829 [Conf]
  2. O. Hauck, M. Garg, Sorin A. Huss
    Two-Phase Asynchronous Wave-Pipelines and Their Application to a 2D-DCT. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:219-0 [Conf]
  3. O. Hauck, A. Katoch, Sorin A. Huss
    VLSI System Design Using Asynchronous Wave Pipelines: A 0.35?m CMOS 1.5 GHz Elliptic Curve Public Key Cryptosystem Chip. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:188-0 [Conf]
  4. Matthias Deegener, Sorin A. Huss
    Software/hardware Co-Design in the MuSE environment. [Citation Graph (0, 0)][DBLP]
    CODES, 1994, pp:195-202 [Conf]
  5. Arshad Jhumka, Stephan Klaus, Sorin A. Huss
    A Dependability-Driven System-Level Design Approach for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:372-377 [Conf]
  6. R. Rosenberger, Sorin A. Huss
    A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:721-728 [Conf]
  7. Stephan Klaus, Sorin A. Huss
    A Novel Specification Model for IP-based Design. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:190-196 [Conf]
  8. Stephan Hermanns, Sorin A. Huss
    Synchronisierungsprobleme von Schaltwerken in Wave Pipelining Architektur und ihre Auswirkungen auf die Wahl der Schaltungstechnik. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:449- [Conf]
  9. O. Hauck, M. Garg, Sorin A. Huss
    Efficient and Safe Asynchronous Wave-Pipeline Architectures for Datapath and Control Unit Applications. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:38-41 [Conf]
  10. Abdulhadi Shoufan, Sorin A. Huss, Murtuza Cutleriwala
    A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:169-183 [Conf]
  11. Uwe F. Baake, Sorin A. Huss
    Scheduling of Signal Transition Graphs under Timing Constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:205-208 [Conf]
  12. Uwe F. Baake, Sorin A. Huss
    Object-oriented representation, analysis, and scheduling of signal transition graphs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2737-2740 [Conf]
  13. Uwe F. Baake, Sorin A. Huss
    Logic Reduction in Timed Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1223-1226 [Conf]
  14. Kaiping Zeng, Sorin A. Huss
    Structure Synthesis of Analog and Mixed-Signal Circuits using Partition Techniques. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:225-230 [Conf]
  15. Kaiping Zeng, Sorin A. Huss
    RAMS: A VHDL-AMS Code Refactoring Tool Supporting High Level Analog Synthesis. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:266-267 [Conf]
  16. Andreas Kühn, Sorin A. Huss
    Dynamically Reconfigurable Hardware for Object-Oriented Processing. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:181-186 [Conf]
  17. Wolfgang Boßung, Sorin A. Huss, Stephan Klaus, Lars Wehmeyer
    Functional Specification of Distributed Digital Image Processing Systems by Process Interface Descriptions. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:2975-2981 [Conf]
  18. Andreas Kühn, Felix Madlener, Sorin A. Huss
    Resource Management for Dynamic Reconfigurable Hardware Structures. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:111-116 [Conf]
  19. M. Ernst, S. Klupsch, O. Hauck, Sorin A. Huss
    Rapid Prototyping for Hardware Accelerated Elliptic Curve Public-Key Cryptosystems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2001, pp:24-31 [Conf]
  20. Michael Jung, Sorin A. Huss
    Fast Points-to Analysis for Languages with Structured Types. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2004, pp:107-121 [Conf]
  21. Michael Jung, Ralf Laue, Sorin A. Huss
    A Case Study on Partial Evaluation in Embedded Software Design. [Citation Graph (0, 0)][DBLP]
    SEUS, 2005, pp:16-21 [Conf]
  22. Michael Goedecke, Sorin A. Huss, Kai Morich
    Automatic Parallelization of the Visual Data-Flow Language Cantata for Efficient Characterization of Analog Circuit Behavior. [Citation Graph (0, 0)][DBLP]
    VL, 1995, pp:69-76 [Conf]
  23. Jens Bieger, Sorin A. Huss, Michael Jung, Stephan Klaus, Thomas Steininger
    Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:577-0 [Conf]
  24. Jens Bieger, Sorin A. Huss
    Konzepte zur Beherrschung der Entwurfskomplexität eingebetteter Systeme. [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2004, v:46, n:2, pp:59-66 [Journal]
  25. M. Ernst, B. Henhapl, S. Klupsch, Sorin A. Huss
    FPGA based hardware acceleration for elliptic curve public key cryptosystems. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 2004, v:70, n:3, pp:299-313 [Journal]
  26. Kaiping Zeng, Sorin A. Huss
    Architecture refinements by code refactoring of behavioral VHDL-AMS models. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  27. S. A. Huss
    Analog circuit synthesis: a search for the Holy Grail? [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  28. Song Yuan, Sorin A. Huss
    Audio watermarking algorithm for real-time speech integrity and authentication. [Citation Graph (0, 0)][DBLP]
    MM&Sec, 2004, pp:220-226 [Conf]

  29. A Novel Processor Architecture for McEliece Cryptosystem and FPGA Platforms. [Citation Graph (, )][DBLP]


  30. Specification and Design Considerations for Reliable Embedded Systems. [Citation Graph (, )][DBLP]


  31. SC-DEVS: An efficient SystemC extension for the DEVS model of computation. [Citation Graph (, )][DBLP]


  32. Compact AES-based Architecture for Symmetric Encryption, Hash Function, and Random Number Generation. [Citation Graph (, )][DBLP]


  33. An efficient reliability evaluation approach for system-level design of embedded systems. [Citation Graph (, )][DBLP]


  34. A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications. [Citation Graph (, )][DBLP]


  35. Schlüsselverwaltung im Sicheren Multicast. [Citation Graph (, )][DBLP]


  36. Reliable Performance Evaluation of Rekeying Algorithms in Secure Multicast. [Citation Graph (, )][DBLP]


  37. Mixed-Level Modeling Using Configurable MOS Transistor Models. [Citation Graph (, )][DBLP]


  38. Real-Time Operating System Services for Realistic SystemC Simulation Models of Embedded Systems. [Citation Graph (, )][DBLP]


  39. A Novel Rekeying Message Authentication Procedure Based on Winternitz OTS and Reconfigurable Hardware Architectures. [Citation Graph (, )][DBLP]


  40. Optimized Implementation of Elliptic Curve Based Additive Homomorphic Encryption for Wireless Sensor Networks [Citation Graph (, )][DBLP]


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