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Peter M. Athanas: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tingting Meng, Peter M. Athanas
    Collaborative Signal Reinforcement in Sensor Networks. [Citation Graph (0, 0)][DBLP]
    AINA, 2007, pp:519-524 [Conf]
  2. Todd B. Fleming, Peter M. Athanas
    Collaborative Synchronization for Signal Reinforcement in Sensor Networks. [Citation Graph (0, 0)][DBLP]
    AINA, 2007, pp:861-868 [Conf]
  3. Peter M. Athanas
    Physical Support for Evolution in Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2002, pp:7- [Conf]
  4. Ray A. Bittner, Peter M. Athanas
    Computing kernels implemented with a wormhole RTR CCM. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:98-105 [Conf]
  5. Jason R. Hess, David C. Lee, Scott J. Harper, Mark T. Jones, Peter M. Athanas
    Implementation and Evaluation of a Prototype Reconfigurable Router. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:44-0 [Conf]
  6. Rhett D. Hudson, David I. Lehn, Peter M. Athanas
    A Run-Time Reconfigurable Engine for Image Interpolation. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:88-95 [Conf]
  7. Neil Steiner, Peter M. Athanas
    An Alternate Wire Database for Xilinx FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:336-337 [Conf]
  8. Jonathan E. Scalera, Creed F. Jones III, Maneesh Soni, Mark B. Bucciero, Peter M. Athanas, A. Lynn Abbott, Amitabh Mishra
    Reconfigurable Object Detection in FLIR Image Sequences. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:284-285 [Conf]
  9. Nabeel Shirazi, Al Walters, Peter M. Athanas
    Quantitative analysis of floating point arithmetic on FPGA based custom computing machines. [Citation Graph (0, 0)][DBLP]
    FCCM, 1995, pp:155-163 [Conf]
  10. Steven Swanchara, Scott J. Harper, Peter M. Athanas
    A Stream-Based Configurable Computing Radio Testbed. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:40-47 [Conf]
  11. Ray A. Bittner, Peter M. Athanas
    Wormhole Run-Time Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:79-85 [Conf]
  12. Peter M. Athanas, A. Lynn Abbott
    Image Processing on a Custom Computing Platform. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:156-167 [Conf]
  13. Jonathan Graf, Peter M. Athanas
    A Key Management Architecture for Securing Off-Chip Data Transfers. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:33-42 [Conf]
  14. Brian Kahne, Peter M. Athanas
    Stream synthesis for a wormhole run-time reconfigurable platform. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:101-110 [Conf]
  15. Alexandra Poetter, Jesse Hunter, Cameron Patterson, Peter M. Athanas, Brent E. Nelson, Neil Steiner
    JHDLBits: The Merging of Two Worlds. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:414-423 [Conf]
  16. Ramana V. Rachakonda, Peter M. Athanas, A. Lynn Abbott
    High-Speed Region Detection and Labeling Using an FPGA Based Custom Computing Platform. [Citation Graph (0, 0)][DBLP]
    FPL, 1995, pp:86-93 [Conf]
  17. Nabeel Shirazi, Peter M. Athanas, A. Lynn Abbott
    Implementation of a 2-D Fast Fourier Transform on an FPGA-Based Custom Computing Machine. [Citation Graph (0, 0)][DBLP]
    FPL, 1995, pp:282-292 [Conf]
  18. Stephen D. Craven, Cameron Patterson, Peter M. Athanas
    A Methodology for Generating Application-Specific Heterogeneous Processor Arrays. [Citation Graph (0, 0)][DBLP]
    HICSS, 2006, pp:- [Conf]
  19. Scott J. Harper, Peter M. Athanas
    A Security Policy Based upon Hardware Encryption. [Citation Graph (0, 0)][DBLP]
    HICSS, 2004, pp:- [Conf]
  20. Anthony J. Mahar, Peter M. Athanas, Stephen D. Craven, Joshua N. Edmison, Jonathan Graf
    Design and Characterization of a Hardware Encryption Management Unit for Secure Computing Platforms. [Citation Graph (0, 0)][DBLP]
    HICSS, 2006, pp:- [Conf]
  21. Steven Swanchara, Peter M. Athanas
    A Methodical Approach for Stream-Oriented Configurable Signal Processing. [Citation Graph (0, 0)][DBLP]
    HICSS, 1999, pp:- [Conf]
  22. Peter M. Athanas, Harvey F. Silverman
    An Adaptive Hardware Machine Architecture and Compiler for Dynamic Processor Reconfiguration. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:397-400 [Conf]
  23. Peter M. Athanas, Harvey F. Silverman
    Amstrong II: A Loosely Coupled Multiprocessor with a Reconfigurable Communications Architecture. [Citation Graph (0, 0)][DBLP]
    IPPS, 1991, pp:385-388 [Conf]
  24. Bharadwaj Pudipeddi, A. Lynn Abbott, Peter M. Athanas
    A Configurable Computing Approach Towards Real-Time Target Tracking. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1998, pp:79-84 [Conf]
  25. Neil Steiner, Peter M. Athanas
    Hardware-Software Interaction: Preliminary Observations. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  26. David C. Lee, Mark T. Jones, Scott F. Midkiff, Peter M. Athanas
    Towards Active Hardware. [Citation Graph (0, 0)][DBLP]
    IWAN, 1999, pp:180-187 [Conf]
  27. Deepak Argarwal, Christopher R. Anderson, Peter M. Athanas
    An 8-GHz Ultra Wideband Transceiver Prototyping Testbed. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:121-127 [Conf]
  28. Ryan J. Fong, Scott J. Harper, Peter M. Athanas
    A Versatile Framework for FPGA Field Updates: An Application of Partial Self-Reconfiguation. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:117-123 [Conf]
  29. Peter M. Athanas, A. Lynn Abbott
    Real-Time Image Processing on a Custom Computing Platform. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1995, v:28, n:2, pp:16-24 [Journal]
  30. Peter M. Athanas, Harvey F. Silverman
    Processor Reconfiguration Through Instruction-Set Metamorphosis. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1993, v:26, n:3, pp:11-18 [Journal]
  31. Jing Ma, Peter M. Athanas, Xin-Ming Huang
    Incremental Design Methodology for Multimillion-gate Fpgas. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:5, pp:1015-1026 [Journal]
  32. Kiran Puttegowda, David I. Lehn, Jae H. Park, Peter M. Athanas, Mark T. Jones
    Context Switching in a Run-Time Reconfigurable System. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2003, v:26, n:3, pp:239-257 [Journal]
  33. Toomas P. Plaks, Peter M. Athanas
    Engineering of Configurable Systems: Guest Editors Foreword. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2003, v:26, n:2, pp:107-108 [Journal]
  34. Toomas P. Plaks, Peter M. Athanas
    Engineering of Configurable Systems, II Guest Editor's Foreword. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2003, v:26, n:3, pp:219-220 [Journal]

  35. The (empty?) Promise of FPGA Supercomputing. [Citation Graph (, )][DBLP]


  36. 06141 Abstracts Collection -- Dynamically Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  37. 06141 Executive Summary -- Dynamically Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  38. Design Productivity for Configurable Computing. [Citation Graph (, )][DBLP]


  39. A Sandbox for Exploring the OpenFire Processor. [Citation Graph (, )][DBLP]


  40. Autonomous Computing Systems: A Proof-of-Concept. [Citation Graph (, )][DBLP]


  41. High-Level Specification of Runtime Reconfigurable Designs. [Citation Graph (, )][DBLP]


  42. Wires On Demand: Run-Time Communication Synthesis for Reconfigurable Computing. [Citation Graph (, )][DBLP]


  43. Application of Self-Configurability for Autonomous, Highly-Localized Self-Regulation. [Citation Graph (, )][DBLP]


  44. Architecturally-Enforced InfoSec in a General-Purpose Self-Configurable System. [Citation Graph (, )][DBLP]


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