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Sofiène Tahar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Amjad Gawanmeh, Sofiène Tahar
    Rank Theorems for Forward Secrecy in Group Key Management Protocols. [Citation Graph (0, 0)][DBLP]
    AINA Workshops (1), 2007, pp:18-23 [Conf]
  2. Amjad Gawanmeh, Sofiène Tahar, Kirsten Winter
    Interfacing ASM with the MDG Tool. [Citation Graph (0, 0)][DBLP]
    Abstract State Machines, 2003, pp:278-292 [Conf]
  3. Tarek Mhamdi, Sofiène Tahar
    Providing Automated Verification in HOL Using MDGs. [Citation Graph (0, 0)][DBLP]
    ATVA, 2004, pp:278-293 [Conf]
  4. Fang Wang, Sofiène Tahar, Otmane Aït Mohamed
    First-Order LTL Model Checking Using MDGs. [Citation Graph (0, 0)][DBLP]
    ATVA, 2004, pp:441-455 [Conf]
  5. Ali Habibi, Sofiène Tahar
    An Approach for the Verification of SystemC Designs Using AsmL. [Citation Graph (0, 0)][DBLP]
    ATVA, 2005, pp:69-83 [Conf]
  6. K. D. Anon, N. Boulerice, Eduard Cerny, Francisco Corella, Michel Langevin, Xiaoyu Song, Sofiène Tahar, Ying Xu, Zijian Zhou
    MDG Tools for the Verification of RTL Designs. [Citation Graph (0, 0)][DBLP]
    CAV, 1996, pp:433-436 [Conf]
  7. Iskander Kort, Sofiène Tahar, Paul Curzon
    Hierarchical Verification Using an MDG-HOL Hybrid Tool. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:244-258 [Conf]
  8. Mohamed Layouni, Jozef Hooman, Sofiène Tahar
    On the Correctness of an Intrusion-Tolerant Group Communication Protocol. [Citation Graph (0, 0)][DBLP]
    CHARME, 2003, pp:231-246 [Conf]
  9. Amr T. Abdel-Hamid, Sofiène Tahar, El Mostapha Aboulhamid
    A Public-Key Watermarking Technique for IP Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:330-335 [Conf]
  10. Ali Habibi, Asif Iqbal Ahmed, Otmane Aït Mohamed, Sofiène Tahar
    On the Design and Verification Methodology of the Look-Aside Interface. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:290-295 [Conf]
  11. Ali Habibi, Asif Iqbal Ahmed, Otmane Aït Mohamed, Sofiène Tahar
    On the Design and Verification Methodology of the Look-Aside Interface. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:290-295 [Conf]
  12. Ali Habibi, Haja Moinudeen, Sofiène Tahar
    Generating finite state machines from SystemC. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:76-81 [Conf]
  13. Ali Habibi, Sofiène Tahar
    Design for Verification of SystemC Transaction Level Models. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:560-565 [Conf]
  14. Ali Habibi, Sofiène Tahar, Amer Samarah, Donglin Li, Otmane Aït Mohamed
    Efficient assertion based verification using TLM. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:106-111 [Conf]
  15. Jounaïdi Ben Hassen, Sofiène Tahar
    On the numerical verification of probabilistic rewriting systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1223-1224 [Conf]
  16. Behzad Akbarpour, Sofiène Tahar
    The Application of Formal Verification to SPW Designs. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:325-333 [Conf]
  17. Ali Habibi, Sofiène Tahar, Adel Ghazel
    Formal Verification of a DSP Chip Using an Iterative Approach. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:12-19 [Conf]
  18. Eduard Cerny, Francisco Corella, Michel Langevin, Xiaoyu Song, Sofiène Tahar, Zijian Zhou
    Verification with Abstract State Machines Using MDGs. [Citation Graph (0, 0)][DBLP]
    Formal Hardware Verification, 1997, pp:79-113 [Conf]
  19. Behzad Akbarpour, Sofiène Tahar
    A Methodology for the Formal Verification of FFT Algorithms in HOL. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2004, pp:37-51 [Conf]
  20. Sofiène Tahar, Paul Curzon, Jianping Lu
    Three Approaches to Hardware Verification: HOL, MDG and VIS Compared. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1998, pp:433-450 [Conf]
  21. Zijian Zhou, Xiaoyu Song, Sofiène Tahar, Eduard Cerny, Francisco Corella, Michel Langevin
    Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:233-247 [Conf]
  22. Abu Nasser M. Abdullah, Behzad Akbarpour, Sofiène Tahar
    Formal Analysis and Verification of an OFDM Modem Design using HOL. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:189-190 [Conf]
  23. Haja Moinudeen, Ali Habibi, Sofiène Tahar
    Design for Verification of the PCI-X Bus. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:187-188 [Conf]
  24. Leila Barakatain, Sofiène Tahar, Jean Lamarche, Jean-Marc Gendreau
    Practical approaches to the verification of a telecom megacell using FormalCheck. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:1-6 [Conf]
  25. Subhashini Balakrishnan, Sofiène Tahar
    A Hierarchical Approach to the Formal Verification of Embedded Systems Using MDGs. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:284-287 [Conf]
  26. Jianping Lu, Sofiène Tahar
    Practical Approaches to the Automatic Verification of an ATM Switch Fabric Using VIS. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:368-0 [Conf]
  27. V. K. Pisini, Sofiène Tahar, Paul Curzon, Otmane Aït Mohamed, Xiaoyu Song
    Formal hardware verification by integrating HOL and MDG. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:23-28 [Conf]
  28. Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny, Michel Langevin
    Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:106-111 [Conf]
  29. Fang Wang, Sofiène Tahar
    Language emptiness checking using MDGs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:88-91 [Conf]
  30. Mohamed H. Zaki, Sofiène Tahar, Guy Bois
    A practical approach for monitoring analog circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:330-335 [Conf]
  31. Jian F. Weng, Guo Q. Xue, Tho Le-Ngoc, Sofiène Tahar
    Analysis of Multilevel-Quantized Soft-Limiting Detector for an FH-SSMA System. [Citation Graph (0, 0)][DBLP]
    ICC (3), 2000, pp:1380-1384 [Conf]
  32. Michel Langevin, Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny
    Behavioral Verification of an ATM Switch Fabric using Implicit Abstract State Enumeration. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:20-26 [Conf]
  33. Hong Peng, Yassine Mokhtari, Sofiène Tahar
    Environment Synthesis for Compositional Model Checking. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:70-0 [Conf]
  34. Sofiène Tahar, Ramayya Kumar
    Towards a Methodology for the Formal Hierarchical Verification. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:58-62 [Conf]
  35. Amr T. Abdel-Hamid, Sofiène Tahar, John Harrison
    Enabling Hardware Verification through Design Changes. [Citation Graph (0, 0)][DBLP]
    ICFEM, 2002, pp:459-470 [Conf]
  36. Behzad Akbarpour, Sofiène Tahar
    Modeling System C Fixed-Point Arithmetic in HOL. [Citation Graph (0, 0)][DBLP]
    ICFEM, 2003, pp:206-225 [Conf]
  37. Hong Peng, Sofiène Tahar, Ferhat Khendek
    SPIN vs. VIS: A Case Study on the Formal Verification of the ATMR Protocol. [Citation Graph (0, 0)][DBLP]
    ICFEM, 2000, pp:79-88 [Conf]
  38. Hong Peng, Sofiène Tahar, Yassine Mokhtari
    Compositional Verification of a Switch Fabric from Nortel Networks. [Citation Graph (0, 0)][DBLP]
    ICFEM, 2003, pp:560-578 [Conf]
  39. M. Hasan Zobair, Sofiène Tahar
    Formal Verification of a SONET Telecom System Block. [Citation Graph (0, 0)][DBLP]
    ICFEM, 2002, pp:447-458 [Conf]
  40. Behzad Akbarpour, Abdelkader Dekdouk, Sofiène Tahar
    Formalization of Cadence SPW Fixed-Point Arithmetic in HOL. [Citation Graph (0, 0)][DBLP]
    IFM, 2002, pp:185-204 [Conf]
  41. Haiyan Xiong, Paul Curzon, Sofiène Tahar, Ann Blandford
    Formally Linking MDG and HOL Based on a Verified MDG System. [Citation Graph (0, 0)][DBLP]
    IFM, 2002, pp:205-224 [Conf]
  42. Jounaïdi Ben Hassen, Sofiène Tahar
    Formal verification of an SoC platform protocol converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:313-316 [Conf]
  43. Ali Habibi, Haja Moinudeen, Amer Samarah, Sofiène Tahar
    Towards a Faster Simulation of SystemC Designs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:418-419 [Conf]
  44. Amr T. Abdel-Hamid, Sofiène Tahar, El Mostapha Aboulhamid
    IP Watermarking Techniques: Survey and Comparison. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:60-65 [Conf]
  45. Ali Habibi, Sofiène Tahar
    A Survey oA Survey on System-On-a-Chip Designn System-On-a-Chip Design. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:212-215 [Conf]
  46. Mostafa Azizi, El Mostapha Aboulhamid, Sofiène Tahar
    Sequential and Distributed Simulations Using Java Threads. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2000, pp:237-243 [Conf]
  47. Mostafa Azizi, El Mostapha Aboulhamid, Sofiène Tahar
    Multithreading-based Coverification Technique of HW/SW Systems. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:1999-2005 [Conf]
  48. Amjad Gawanmeh, Sofiène Tahar, Kirsten Winter
    Formal Verification of ASM Designs Using the MDG Tool. [Citation Graph (0, 0)][DBLP]
    SEFM, 2003, pp:210-219 [Conf]
  49. Behzad Akbarpour, Sofiène Tahar
    Error Analysis of Digital Filters Using Theorem Proving. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 2004, pp:1-17 [Conf]
  50. Sofiène Tahar, Paul Curzon
    A Comparison of MDG and HOL for Hardware Verification. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1996, pp:415-430 [Conf]
  51. Sofiène Tahar, Ramayya Kumar
    Implementing a Methodology for Formally Verifying RISC Processors in HOL. [Citation Graph (0, 0)][DBLP]
    HUG, 1993, pp:281-294 [Conf]
  52. Sofiène Tahar, Ramayya Kumar
    Implementational Issues for Verifying RISC-Pipeline Conflicts in HOL. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1994, pp:424-439 [Conf]
  53. Haiyan Xiong, Paul Curzon, Sofiène Tahar
    Importing MDG Verification Results into HOL. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1999, pp:293-310 [Conf]
  54. Amr T. Abdel-Hamid, Sofiène Tahar, El Mostapha Aboulhamid
    Finite State Machine IP Watermarking: A Tutorial. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:457-464 [Conf]
  55. Sofiène Tahar, Ramayya Kumar
    Formal Specification and Verification Techniques for RISC Pipeline Conflicts. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1995, v:38, n:2, pp:111-120 [Journal]
  56. Ali Habibi, Sofiène Tahar
    On the Transformation of SystemC to AsmL Using Abstract Interpretation. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2005, v:131, n:, pp:39-49 [Journal]
  57. Behzad Akbarpour, Sofiène Tahar, Abdelkader Dekdouk
    Formalization of Fixed-Point Arithmetic in HOL. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2005, v:27, n:1-2, pp:173-200 [Journal]
  58. Sofiène Tahar, Ramayya Kumar
    A Practical Methodology for the Formal Verification of RISC Processors. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1998, v:13, n:2, pp:159-225 [Journal]
  59. Otmane Aït Mohamed, Xiaoyu Song, Eduard Cerny, Sofiène Tahar, Zijian Zhou
    MDG-Based State Enumeration By Retiming And Circuit Transformation. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2004, v:13, n:5, pp:1111-1132 [Journal]
  60. Sofiène Tahar, Paul Curzon
    Comparing HOL and MDG: a Case Study on the Verification of an ATM Switch Fabric. [Citation Graph (0, 0)][DBLP]
    Nord. J. Comput., 1999, v:6, n:4, pp:372-402 [Journal]
  61. Skander Kort, Sofiène Tahar, Paul Curzon
    Hierarchical formal verification using a hybrid tool. [Citation Graph (0, 0)][DBLP]
    STTT, 2003, v:4, n:3, pp:313-322 [Journal]
  62. Hong Peng, Sofiène Tahar, Ferhat Khendek
    Comparison of SPIN and VIS for protocol verification. [Citation Graph (0, 0)][DBLP]
    STTT, 2003, v:4, n:2, pp:234-245 [Journal]
  63. Behzad Akbarpour, Sofiène Tahar
    An approach for the formal verification of DSP designs using Theorem proving. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1441-1457 [Journal]
  64. Sofiène Tahar, Xiaoyu Song, Eduard Cerny, Zijian Zhou, Michel Langevin, Otmane Aït Mohamed
    Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:956-972 [Journal]
  65. Ali Habibi, Sofiène Tahar
    Design and verification of SystemC transaction-level models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:57-68 [Journal]
  66. Rabeb Mizouni, Sofiène Tahar, Paul Curzon
    Hybrid verification integrating HOL theorem proving with MDG model checking. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:11, pp:1200-1207 [Journal]
  67. Ali Habibi, Sofiène Tahar
    AsmL Semantics in Fixpoint. [Citation Graph (0, 0)][DBLP]
    Abstract State Machines, 2005, pp:233-246 [Conf]
  68. Amjad Gawanmeh, Ali Habibi, Sofiène Tahar
    Embedding and Verification of PSL using AsmL. [Citation Graph (0, 0)][DBLP]
    Abstract State Machines, 2005, pp:201-216 [Conf]
  69. Osman Hasan, Sofiène Tahar
    Formalization of Continuous Probability Distributions. [Citation Graph (0, 0)][DBLP]
    CADE, 2007, pp:3-18 [Conf]
  70. Ghiath Al-Sammane, Mohamed H. Zaki, Sofiène Tahar
    A symbolic methodology for the verification of analog and mixed signal designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:249-254 [Conf]
  71. Mohamed H. Zaki, Ghiath Al-Sammane, Sofiène Tahar
    Formal Verification of Analog and Mixed Signal Designs in Mathematica. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science (2), 2007, pp:263-267 [Conf]
  72. Osman Hasan, Sofiène Tahar
    Verification of Probabilistic Properties in HOL Using the Cumulative Distribution Function. [Citation Graph (0, 0)][DBLP]
    IFM, 2007, pp:333-352 [Conf]
  73. Osman Hasan, Sofiène Tahar
    Verification of Expectation Properties for Discrete Random Variables in HOL. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 2007, pp:119-134 [Conf]
  74. Haiyan Xiong, Paul Curzon, Sofiène Tahar, Ann Blandford
    Providing a formal linkage between MDG and HOL. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2007, v:30, n:2, pp:83-116 [Journal]
  75. Osman Hasan, Sofiène Tahar
    Formalization of the Standard Uniform random variable. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 2007, v:382, n:1, pp:71-83 [Journal]

  76. Formal Probabilistic Analysis: A Higher-Order Logic Based Approach. [Citation Graph (, )][DBLP]


  77. Formal verification of analog circuits in the presence of noise and process variation. [Citation Graph (, )][DBLP]


  78. Formal verification of pipeline conflicts in RISC processors. [Citation Graph (, )][DBLP]


  79. Formal Reasoning about Expectation Properties for Continuous Random Variables. [Citation Graph (, )][DBLP]


  80. Formal verification of analog designs using MetiTarski. [Citation Graph (, )][DBLP]


  81. Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs. [Citation Graph (, )][DBLP]


  82. A New Approach for the Construction of Multiway Decision Graphs. [Citation Graph (, )][DBLP]


  83. Formal Probabilistic Analysis of Stuck-at Faults in Reconfigurable Memory Arrays. [Citation Graph (, )][DBLP]


  84. Radio Access Network traffic generation for Mobile Switching Center. [Citation Graph (, )][DBLP]


  85. Qualitative Abstraction based Verification for Analog Circuits. [Citation Graph (, )][DBLP]


  86. Performance Analysis of ARQ Protocols using a Theorem Prover. [Citation Graph (, )][DBLP]


  87. Event-B based invariant checking of secrecy in group key protocols. [Citation Graph (, )][DBLP]


  88. Formal Analysis of Optical Waveguides in HOL. [Citation Graph (, )][DBLP]


  89. Formal Lifetime Reliability Analysis Using Continuous Random Variables. [Citation Graph (, )][DBLP]


  90. Autometic Generation of SystemC Transactors from AsmL Specification. [Citation Graph (, )][DBLP]


  91. Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSL. [Citation Graph (, )][DBLP]


  92. Enabling SystemC Verification using Abstract State Machines. [Citation Graph (, )][DBLP]


  93. On the Formalization of the Lebesgue Integration Theory in HOL. [Citation Graph (, )][DBLP]


  94. Verifying a Synthesized Implementation of IEEE-754 Floating-Point Exponential Function using HOL. [Citation Graph (, )][DBLP]


  95. Probabilistic Analysis of Wireless Systems Using Theorem Proving. [Citation Graph (, )][DBLP]


  96. Error Analysis and Verification of an IEEE 802.11 OFDM Modem using Theorem Proving. [Citation Graph (, )][DBLP]


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