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Paolo Bernardi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Paolo Bernardi, Claudio Demartini, Filippo Gandino, Bartolomeo Montrucchio, Maurizio Rebaudengo, Erwing Ricardo Sanchez
    Agri-Food Traceability Management using a RFID System with Privacy Protection. [Citation Graph (0, 0)][DBLP]
    AINA, 2007, pp:68-75 [Conf]
  2. Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda
    Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:228-233 [Conf]
  3. M. Bellato, Paolo Bernardi, D. Bortolato, A. Candelori, M. Ceschia, A. Paccagnella, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, P. Zambolin
    Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:584-589 [Conf]
  4. Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda
    Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:228-233 [Conf]
  5. Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10720-10725 [Conf]
  6. Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda
    An effective technique for minimizing the cost of processor software-based diagnosis in SoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:412-417 [Conf]
  7. Paolo Bernardi, Michelangelo Grosso
    Test Considerations about the Structured ASIC Paradigm. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:232-233 [Conf]
  8. Paolo Bernardi, Leticia Maria Veiras Bolzani, Matteo Sonza Reorda
    Extended Fault Detection Techniques for Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:55-60 [Conf]
  9. Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:445-453 [Conf]
  10. Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda
    Exploiting an I-IP for In-Field SOC Test. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:404-412 [Conf]
  11. Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
    On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core. [Citation Graph (0, 0)][DBLP]
    DSN, 2005, pp:50-58 [Conf]
  12. Paolo Bernardi, Filippo Gandino, Bartolomeo Montrucchio, Maurizio Rebaudengo, Erwing Ricardo Sanchez
    Design of an UHF RFID transponder for secure authentication. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:387-392 [Conf]
  13. Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda
    Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:411-416 [Conf]
  14. Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante
    On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:115-120 [Conf]
  15. Alberto Manzone, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Ernesto Sánchez, Matteo Sonza Reorda
    Integrating BIST Techniques for On-Line SoC Testing. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:235-240 [Conf]
  16. Massimo Violante, M. Ceschia, Matteo Sonza Reorda, A. Paccagnella, Paolo Bernardi, Maurizio Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori
    Analyzing SEU Effects in SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:119-123 [Conf]
  17. Davide Appello, Paolo Bernardi, Alessandra Fudoli, Maurizio Rebaudengo, Matteo Sonza Reorda, Vincenzo Tancorre, Massimo Violante
    Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:379-385 [Conf]
  18. Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
    Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:55-62 [Conf]
  19. Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda
    Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:22-27 [Conf]
  20. Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero
    Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:37-41 [Conf]
  21. Paolo Bernardi, Leticia Maria Veiras Bolzani, Alberto Manzone, Marcella Guagliumi Massimo Osella, Massimo Violante, Matteo Sonza Reorda
    Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:3-8 [Conf]
  22. Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
    A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:386-391 [Conf]
  23. Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
    On the Automation of the Test Flow of Complex SoCs. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:166-171 [Conf]
  24. Davide Appello, Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda
    System-in-Package Testing: Problems and Solutions. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:3, pp:203-211 [Journal]
  25. Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
    A New Hybrid Fault Detection Technique for Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:185-198 [Journal]
  26. Paolo Bernardi, M. Cavagnaro, S. Pisa
    Assessment of the potential risk for humans exposed to millimeter-wave wireless LANs: the power absorbed in the eye. [Citation Graph (0, 0)][DBLP]
    Wireless Networks, 1997, v:3, n:6, pp:511-517 [Journal]
  27. James C. Lin, Paolo Bernardi
    Editorial: Exposure Hazards and Health Protectionin Personal Communication Services. [Citation Graph (0, 0)][DBLP]
    Wireless Networks, 1997, v:3, n:6, pp:435-437 [Journal]
  28. Paolo Bernardi, Leticia Maria Veiras Bolzani, Matteo Sonza Reorda
    A Hybrid Approach to Fault Detection and Correction in SoCs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:107-112 [Conf]
  29. Paolo Bernardi, Michelangelo Grosso, E. Sanchez, Matteo Sonza Reorda
    On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:179-184 [Conf]
  30. Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda
    Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  31. An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers. [Citation Graph (, )][DBLP]


  32. An efficient fault simulation technique for transition faults in non-scan sequential circuits. [Citation Graph (, )][DBLP]


  33. SoC Symbolic Simulation: a case study on delay fault testing. [Citation Graph (, )][DBLP]


  34. An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs. [Citation Graph (, )][DBLP]


  35. An Exact and Efficient Critical Path Tracing Algorithm. [Citation Graph (, )][DBLP]


  36. An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains. [Citation Graph (, )][DBLP]


  37. Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors. [Citation Graph (, )][DBLP]


  38. An I-IP based approach for the monitoring of NBTI effects in SoCs. [Citation Graph (, )][DBLP]


  39. Evaluating Alpha-induced soft errors in embedded microprocessors. [Citation Graph (, )][DBLP]


  40. An optimized hybrid approach to provide fault detection and correction in SoCs. [Citation Graph (, )][DBLP]


  41. A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions. [Citation Graph (, )][DBLP]


  42. An adaptive tester architecture for volume diagnosis. [Citation Graph (, )][DBLP]


  43. Automatic Functional Stress Pattern Generation for SoC Reliability Characterization. [Citation Graph (, )][DBLP]


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