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Maurizio Rebaudengo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Paolo Bernardi, Claudio Demartini, Filippo Gandino, Bartolomeo Montrucchio, Maurizio Rebaudengo, Erwing Ricardo Sanchez
    Agri-Food Traceability Management using a RFID System with Privacy Protection. [Citation Graph (0, 0)][DBLP]
    AINA, 2007, pp:68-75 [Conf]
  2. Davide Appello, Fulvio Corno, M. Giovinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:97-102 [Conf]
  3. Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    Guaranteeing Testability in Re-encoding for Low Power. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:30-35 [Conf]
  4. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    FPGA-Based Fault Injection for Microprocessor Systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:304-0 [Conf]
  5. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero
    A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:56-61 [Conf]
  6. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:68-73 [Conf]
  7. Mario Baldi, Fulvio Corno, Maurizio Rebaudengo, Paolo Prinetto, Matteo Sonza Reorda, Giovanni Squillero
    Simulation-based verification of network protocols performance. [Citation Graph (0, 0)][DBLP]
    CHARME, 1997, pp:236-251 [Conf]
  8. Marcello Lajolo, Luciano Lavagno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Automatic test bench generation for simulation-based validation. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:136-140 [Conf]
  9. M. Bellato, Paolo Bernardi, D. Bortolato, A. Candelori, M. Ceschia, A. Paccagnella, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, P. Zambolin
    Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:584-589 [Conf]
  10. Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10720-10725 [Conf]
  11. Ph. Cheynet, B. Nicolescu, Raoul Velazco, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    System safety through automatic high-level code transformations: an experimental evaluation. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:297-301 [Conf]
  12. Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno
    Evaluating System Dependability in a Co-Design Framework. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:586-590 [Conf]
  13. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10602-10607 [Conf]
  14. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:250-258 [Conf]
  15. Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaudengo, Massimo Violante
    Optimal Vector Selection for Low Power BIST. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:219-226 [Conf]
  16. Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar
    Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:212-217 [Conf]
  17. Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda, Pierluigi Civera
    An Integrated HW and SW Fault Injection Environment for Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:117-0 [Conf]
  18. Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:445-453 [Conf]
  19. Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda
    Exploiting an I-IP for In-Field SOC Test. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:404-412 [Conf]
  20. O. Goloubeva, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Soft-Error Detection Using Control Flow Assertions. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:581-588 [Conf]
  21. Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante
    An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:257-265 [Conf]
  22. Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante
    Soft-Error Detection through Software Fault-Tolerance Techniques. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:210-218 [Conf]
  23. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    A New Functional Fault Model for FPGA Application-Oriented Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:372-380 [Conf]
  24. Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto
    Combined software and hardware techniques for the design of reliable IP processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:265-273 [Conf]
  25. Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
    On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core. [Citation Graph (0, 0)][DBLP]
    DSN, 2005, pp:50-58 [Conf]
  26. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Maurizio Damiani, Leonardo Impagliazzo, G. Sartore
    On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications. [Citation Graph (0, 0)][DBLP]
    EDCC, 1996, pp:190-202 [Conf]
  27. Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Prediction of Power Requirements for High-Speed Circuits. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2000, pp:247-254 [Conf]
  28. Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Test Pattern Generation Under Low Power Constraints. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 1999, pp:162-170 [Conf]
  29. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:493-502 [Conf]
  30. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:607-615 [Conf]
  31. Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    ALPS: A Peak Power Estimation Tool for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:350-353 [Conf]
  32. Paolo Bernardi, Filippo Gandino, Bartolomeo Montrucchio, Maurizio Rebaudengo, Erwing Ricardo Sanchez
    Design of an UHF RFID transponder for secure authentication. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:387-392 [Conf]
  33. F. Bianchi, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Roberto Ansaloni
    Boolean Function Manipulation on a Parallel System Using BDDs. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1997, pp:916-928 [Conf]
  34. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1996, pp:454-459 [Conf]
  35. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva
    A PVM tool for automatic test generation on parallel and distributed systems. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1995, pp:39-44 [Conf]
  36. P. P. Delsanto, S. Biancotto, M. Scalerandi, Maurizio Rebaudengo, Matteo Sonza Reorda
    Exploiting massively parallel architectures for the solution of diffusion and propagation problems. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1995, pp:1-6 [Conf]
  37. Gavril Godza, Maurizio Rebaudengo, Matteo Sonza Reorda
    Using Parallel Genetic Algorithms for Solving the Min-Cut Problem. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1996, pp:985-986 [Conf]
  38. Maurizio Rebaudengo, Matteo Sonza Reorda
    A Cellular Genetic Algorithm for the Floorplan Area Optimization Problem on a SIMD Architecture. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1996, pp:987-988 [Conf]
  39. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero
    A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:381-386 [Conf]
  40. Matteo Sonza Reorda, Maurizio Rebaudengo
    A Genetic Algorithm for Floorplan Area Optimization. [Citation Graph (0, 0)][DBLP]
    International Conference on Evolutionary Computation, 1994, pp:93-96 [Conf]
  41. Mario Baldi, Fulvio Corno, Maurizio Rebaudengo, Giovanni Squillero
    GA-Based Performance Analysis of Network Protocols. [Citation Graph (0, 0)][DBLP]
    ICTAI, 1997, pp:118-124 [Conf]
  42. S. Chuisano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization. [Citation Graph (0, 0)][DBLP]
    ICTAI, 1997, pp:133-0 [Conf]
  43. Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva
    GATTO: An Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ICTAI, 1994, pp:411-417 [Conf]
  44. Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda
    A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:206-210 [Conf]
  45. Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
    Hybrid Soft Error Detection by Means of Infrastructure IP Cores. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:79-88 [Conf]
  46. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Exploiting FPGA for Accelerating Fault Injection Experiments. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:9-13 [Conf]
  47. B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    New Techniques for Accelerating Fault Injection in VHDL Descriptions. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:61-66 [Conf]
  48. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Analysis of SEU Effects in a Pipelined Processor. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:112-116 [Conf]
  49. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Ph. Cheynet, B. Nicolescu, Raoul Velazco
    Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:17-0 [Conf]
  50. Alberto Manzone, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Ernesto Sánchez, Matteo Sonza Reorda
    Integrating BIST Techniques for On-Line SoC Testing. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:235-240 [Conf]
  51. Massimo Violante, M. Ceschia, Matteo Sonza Reorda, A. Paccagnella, Paolo Bernardi, Maurizio Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori
    Analyzing SEU Effects in SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:119-123 [Conf]
  52. Davide Appello, Paolo Bernardi, Alessandra Fudoli, Maurizio Rebaudengo, Matteo Sonza Reorda, Vincenzo Tancorre, Massimo Violante
    Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:379-385 [Conf]
  53. Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    A fault injection environment for microprocessor-based boards. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:768-773 [Conf]
  54. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    Comparing Topological, Symbolic and GA-based ATPGs: An Experimental Approach. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:39-47 [Conf]
  55. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:558-564 [Conf]
  56. Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:240-249 [Conf]
  57. Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda
    A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:12-16 [Conf]
  58. Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
    Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:55-62 [Conf]
  59. Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda
    Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:22-27 [Conf]
  60. Silvano Gai, Maurizio Rebaudengo, Matteo Sonza Reorda
    An improved data parallel algorithm for Boolean function manipulation using BDDs. [Citation Graph (0, 0)][DBLP]
    PDP, 1995, pp:33-41 [Conf]
  61. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits. [Citation Graph (0, 0)][DBLP]
    PPSN, 1996, pp:792-800 [Conf]
  62. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    SAARA: a simulated annealing algorithm for test pattern generation for digital circuits. [Citation Graph (0, 0)][DBLP]
    SAC, 1997, pp:228-232 [Conf]
  63. Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda
    FlexFi: A Flexible Fault Injection Environment for Microprocessor-Based Systems. [Citation Graph (0, 0)][DBLP]
    SAFECOMP, 1999, pp:323-335 [Conf]
  64. B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Speeding-Up Fault Injection Campaigns in VHDL Models. [Citation Graph (0, 0)][DBLP]
    SAFECOMP, 2000, pp:27-36 [Conf]
  65. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Marco Torchiano
    A Source-to-Source Compiler for Generating Dependable Software. [Citation Graph (0, 0)][DBLP]
    SCAM, 2001, pp:35-44 [Conf]
  66. Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
    A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:386-391 [Conf]
  67. Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
    On the Automation of the Test Flow of Complex SoCs. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:166-171 [Conf]
  68. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    A Test Pattern Generation Methodology for Low-Power Consumption. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:453-459 [Conf]
  69. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva
    A portable ATPG tool for parallel and distributed systems. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:29-34 [Conf]
  70. Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
    Low Power BIST via Non-Linear Hybrid Cellular Automata. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:29-34 [Conf]
  71. Maurizio Rebaudengo, Matteo Sonza Reorda
    Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM . [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:452-459 [Conf]
  72. Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda
    Fault Injection for Embedded Microprocessor-based Systems. [Citation Graph (0, 0)][DBLP]
    J. UCS, 1999, v:5, n:10, pp:693-711 [Journal]
  73. Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
    A New Hybrid Fault Detection Technique for Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:185-198 [Journal]
  74. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:991-1000 [Journal]
  75. Maurizio Rebaudengo, Matteo Sonza Reorda
    GALLO: a genetic algorithm for floorplan area optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:943-951 [Journal]
  76. Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    EXFI: a low-cost fault injection system for embedded microprocessor-based boards. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:4, pp:626-634 [Journal]
  77. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero
    Initializability analysis of synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:2, pp:249-264 [Journal]
  78. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    New techniques for efficiently assessing reliability of SOCs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:1, pp:53-61 [Journal]

  79. New static compaction techniques of test sequences for sequential circuits. [Citation Graph (, )][DBLP]


  80. A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs. [Citation Graph (, )][DBLP]


  81. Safety Evaluation of NanoFabrics. [Citation Graph (, )][DBLP]


  82. Introducing Probability in RFID Reader-to-Reader Anti-collision. [Citation Graph (, )][DBLP]


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