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Publications of Author

1. Takuo Nakashima, Toshinori Sueyoshi
   Self-Similar Property for TCP Traffic under the Bottleneck Restrainment. [Citation Graph (0, 0)][DBLP]
   AINA Workshops (1), 2007, pp:228-233 [Conf]
   
2. Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi
   Effective clustering technique to optimize routability of outer cluster nets. [Citation Graph (0, 0)][DBLP]
   FPGA, 2006, pp:229- [Conf]
   
3. Hisashi Tsukiashi, Masahiro Iida, Toshinori Sueyoshi
   Applying the Small-World Network to Routing Structure of FPGAs. [Citation Graph (0, 0)][DBLP]
   FPL, 2005, pp:65-70 [Conf]
   
4. Kazuaki Murakami, Shin-ichiro Mori, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita
   The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures. [Citation Graph (0, 0)][DBLP]
   ICS, 1989, pp:351-360 [Conf]
   
5. Kazuaki Murakami, Shin-ichiro Mori, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita
   The Kyushu University Reconfigurable Parallel Processor - Design Philosophy and Architecture. [Citation Graph (0, 0)][DBLP]
   IFIP Congress, 1989, pp:995-1000 [Conf]
   
6. Yulu Yang, Hideharu Amano, Hidetomo Shibamura, Toshinori Sueyoshi
   Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers. [Citation Graph (0, 0)][DBLP]
   SPDP, 1993, pp:591-595 [Conf]
   
7. Toshinori Sueyoshi, Morihiro Kuga, Hidetomo Shibamura
   KITE microprocessor and CAE for computer science. [Citation Graph (0, 0)][DBLP]
   Systems and Computers in Japan, 2002, v:33, n:8, pp:64-74 [Journal]
   
8. Yulu Yang, Akira Funahashi, Akiya Jouraku, Hiroaki Nishi, Hideharu Amano, Toshinori Sueyoshi
   Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Parallel Distrib. Syst., 2001, v:12, n:7, pp:701-715 [Journal]
   
9. Motoki Amagasaki, Takurou Shimokawa, Kazunori Matsuyama, Ryoichi Yamaguchi, Hideaki Nakayama, Naoto Hamabe, Masahiro Iida, Toshinori Sueyoshi
   Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device. [Citation Graph (0, 0)][DBLP]
   VLSI-SoC, 2006, pp:198-203 [Conf]
   
10. Kazunori Matsuyama, Motoki Amagasaki, Hideaki Nakayama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi
    Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:142-154 [Conf]
    
11. 
    Analysis of Queueing Property for Self-Similar Traffic. [Citation Graph (, )][DBLP]
    
    
12. 
    A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic. [Citation Graph (, )][DBLP]
    
    
13. 
    A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic. [Citation Graph (, )][DBLP]
    
    
14. 
    A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores. [Citation Graph (, )][DBLP]
    
    
15. 
    A novel states recovery technique for the TMR softcore processor. [Citation Graph (, )][DBLP]
    
    
16. 
    Improvement of Execution Efficiency on the MX Core. [Citation Graph (, )][DBLP]
    
    
17. 
    A Novel Local Interconnect Architecture for Variable Grain Logic Cell. [Citation Graph (, )][DBLP]
    
    
18. 
    Memory Sharing Approach for TMR Softcore Processor. [Citation Graph (, )][DBLP]
    
    
19. 
    Performance Estimation of TCP under SYN Flood Attacks. [Citation Graph (, )][DBLP]
    
    
20. 
    Extraction of Characteristics of Anomaly Accessed IP Packets by the Entropy-Based Analysis. [Citation Graph (, )][DBLP]
    
    
21. 
    Early DoS/DDoS Detection Method using Short-term Statistics. [Citation Graph (, )][DBLP]