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Aristides Efthymiou: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rahman Hassan, Antony Harris, Nigel P. Topham, Aristides Efthymiou
    Synthetic Trace-Driven Simulation of Cache Memory. [Citation Graph (0, 0)][DBLP]
    AINA Workshops (1), 2007, pp:764-771 [Conf]
  2. Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou
    A Low-Power Processor Architecture Optimized forWireless Devices. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:185-190 [Conf]
  3. Aristides Efthymiou, Jim D. Garside
    Adaptive Pipeline Structures fo Speculation Control. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:46-55 [Conf]
  4. Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury
    An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:207-215 [Conf]
  5. Aristides Efthymiou, John Bainbridge, Douglas A. Edwards
    Adding Testability to an Asynchronous Interconnect for GALS SoC. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:20-23 [Conf]
  6. Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards
    Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:672-673 [Conf]
  7. Aristides Efthymiou
    Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:377-382 [Conf]
  8. Aristides Efthymiou, Jim D. Garside
    Adaptive Pipeline Depth Control for Processor Power-Management. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:454-457 [Conf]
  9. S. Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou
    Fast, Parallel Two-Rail Code Checker with Enhanced Testability. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:149-156 [Conf]
  10. Aristides Efthymiou, Jim D. Garside
    An adaptive serial-parallel CAM architecture for low-power cache blocks. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:136-141 [Conf]
  11. Manolis Katevenis, Panagiota Vatsolaki, Aristides Efthymiou
    Pipelined Memory Shared Buffer for VLSI Switches. [Citation Graph (0, 0)][DBLP]
    SIGCOMM, 1995, pp:39-48 [Conf]
  12. Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple
    Power Management in the Amulet Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:2, pp:42-52 [Journal]
  13. Aristides Efthymiou, Jim D. Garside
    A CAM with mixed serial-parallel comparison for use in low energy caches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:325-329 [Journal]
  14. Aristides Efthymiou, John Bainbridge, Douglas A. Edwards
    Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1384-1393 [Journal]

  15. A Partial Scan Based Test Generation for Asynchronous Circuits. [Citation Graph (, )][DBLP]


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