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Robert Wille: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kevin Bolding, Sen-Ching Cheung, Sung-Eun Choi, Carl Ebeling, Soha Hassoun, Ton Anh Ngo, Robert Wille
    The chaos router chip: design and implementation of an adaptive router. [Citation Graph (0, 0)][DBLP]
    VLSI, 1993, pp:311-320 [Conf]

  2. BDD-based synthesis of reversible logic for large functions. [Citation Graph (, )][DBLP]

  3. Reducing the number of lines in reversible circuits. [Citation Graph (, )][DBLP]

  4. Quantified Synthesis of Reversible Logic. [Citation Graph (, )][DBLP]

  5. Debugging of Toffoli networks. [Citation Graph (, )][DBLP]

  6. Verifying UML/OCL models using Boolean satisfiability. [Citation Graph (, )][DBLP]

  7. Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. [Citation Graph (, )][DBLP]

  8. Synthesizing Reversible Circuits for Irreversible Functions. [Citation Graph (, )][DBLP]

  9. Graph Transformation Units Guided by a SAT Solver. [Citation Graph (, )][DBLP]

  10. Contradictory antecedent debugging in bounded model checking. [Citation Graph (, )][DBLP]

  11. Enhancing debugging of multiple missing control errors in reversible logic. [Citation Graph (, )][DBLP]

  12. Fast exact Toffoli network synthesis of reversible logic. [Citation Graph (, )][DBLP]

  13. Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. [Citation Graph (, )][DBLP]

  14. RevLib: An Online Resource for Reversible Functions and Reversible Circuits. [Citation Graph (, )][DBLP]

  15. Evaluation of Cardinality Constraints on SMT-Based Debugging. [Citation Graph (, )][DBLP]

  16. Equivalence Checking of Reversible Circuits. [Citation Graph (, )][DBLP]

  17. Reducing Reversible Circuit Cost by Adding Lines. [Citation Graph (, )][DBLP]

  18. Efficient Simulation-Based Debugging of Reversible Logic. [Citation Graph (, )][DBLP]

  19. Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. [Citation Graph (, )][DBLP]

  20. SWORD: A SAT like prover using word level information. [Citation Graph (, )][DBLP]

  21. Reversible Logic Synthesis with Output Permutation. [Citation Graph (, )][DBLP]

  22. Contradiction Analysis for Constraint-based Random Simulation. [Citation Graph (, )][DBLP]

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