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Hannu Tenhunen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yuechao Niu, Majid Baghaei Nejad, Hannu Tenhunen, Li-Rong Zheng
    Design of a Digital Baseband Processor for UWB Transceiver on RFID Tag. [Citation Graph (0, 0)][DBLP]
    AINA Workshops (2), 2007, pp:358-361 [Conf]
  2. Li-Rong Zheng, Hannu Tenhunen
    Noise Margin Constraints for Interconnectivity in Deep Submicron Low Power and Mixed-Signal VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1999, pp:123-136 [Conf]
  3. Jouni Isoaho, Arto Nummela, Hannu Tenhunen
    Technologies and Utilization fo Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:11-25 [Conf]
  4. Jouni Isoaho, Axel Jantsch, Hannu Tenhunen
    DSP Development with Full-Speed Prototyping Based on HW/SW Codesign Techniques. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:318-320 [Conf]
  5. T. Saluvere, D. Kerek, Hannu Tenhunen
    Direct Sequence Spread Spectrum Digital Radio DSP Prototyping Using Xilinx FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:138-140 [Conf]
  6. Tuomas Valtonen, Jouni Isoaho, Hannu Tenhunen
    The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:816-825 [Conf]
  7. Elena Dubrova, Maxim Teslenko, Hannu Tenhunen
    Computing attractors in dynamic networks. [Citation Graph (0, 0)][DBLP]
    IADIS AC, 2005, pp:535-542 [Conf]
  8. Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen
    Analytic Modeling of Interconnects for Deep Sub-Micron Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:835-842 [Conf]
  9. Eero Pajarre, Tapani Ritoniemi, Hannu Tenhunen
    Methods and Algorithms for Converting IC Designs Between Incompatible Design Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:34-37 [Conf]
  10. Bingxin Li, Hannu Tenhunen
    A Design of Operational Amplifier for Sigma Delta Modulators Using 0.35um CMOS Process. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:23-34 [Conf]
  11. Xinzhong Duo, Li-Rong Zheng, Hannu Tenhunen
    RF robustness enhancement through statistical analysis of chip package co-design. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:988-991 [Conf]
  12. Andreas Gothenberg, Hannu Tenhunen
    Performance analysis of sampling switches in voltage and frequency domains using Volterra series. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:765-768 [Conf]
  13. Jian Liu, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
    A global wire planning scheme for Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:892-895 [Conf]
  14. Wim Michielsen, Li-Rong Zheng, Hannu Tenhunen
    Analysis and design of a double tuned Clapp oscillator for multi-band multi-standard radio. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:681-684 [Conf]
  15. M. Rinne, T. Jarske, Hannu Tenhunen, Olli Vainio, Yrjö Neuvo
    Noise Suppression System Integration Using an Analog Allpass Filter Bank. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1207-1210 [Conf]
  16. Meigen Shen, Li-Rong Zheng, Hannu Tenhunen
    Case study of cost and performance trade-off analysis for mixed-signal integration in system-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:585-588 [Conf]
  17. Meigen Shen, Li-Rong Zheng, Esa Tjukanoff, Jouni Isoaho, Hannu Tenhunen
    Case study of interconnect analysis for standing wave oscillator design. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:456-459 [Conf]
  18. Bingxin Li, Hannu Tenhunen
    Sigma delta modulators using semi-uniform quantizers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:456-459 [Conf]
  19. Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi
    Energy efficient signaling in DSM CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:411-414 [Conf]
  20. Imed Ben Dhaou, N. Money, Hannu Tenhunen
    Fast low-power characterization of arithmetic units in DSM CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:531-534 [Conf]
  21. T. Suutari, Jouni Isoaho, Hannu Tenhunen
    High-speed serial communication with error correction using 0.25 um CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:618-621 [Conf]
  22. Lihong Jia, Yonghong Gao, Jouni Isoaho, Hannu Tenhunen
    Design of a super-pipelined Viterbi decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:133-136 [Conf]
  23. Imed Ben Dhaou, Hannu Tenhunen
    Combinatorial architectural level power optimization for a class of orthogonal transforms. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:70-75 [Conf]
  24. Li-Rong Zheng, Hannu Tenhunen
    Effective power and ground distribution scheme for deep submicron high speed VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:537-540 [Conf]
  25. B. E. Jonsson, Hannu Tenhunen
    A 3 V switched-current pipelined analog-to-digital converter in a 5 V CMOS process. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:351-354 [Conf]
  26. B. E. Jonsson, Hannu Tenhunen
    A dual 3-V 32-MS/s CMOS switched-current ADC for telecommunication applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:343-346 [Conf]
  27. Thomas Meincke, Ahmed Hemani, Shashi Kumar, Peeter Ellervee, Johnny Öberg, Thomas Olsson, Peter Nilsson, Dan Lindqvist, Hannu Tenhunen
    Globally asynchronous locally synchronous architecture for large high-performance ASICs. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:512-515 [Conf]
  28. L. Horvath, Imed Ben Dhaou, Hannu Tenhunen, Jouni Isoaho
    A novel, high-speed, reconfigurable demapper-symbol deinterleaver architecture for DVB-T. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 1999, pp:382-385 [Conf]
  29. P. Eriksson, Hannu Tenhunen
    A model for predicting sampler RF bandwidth and conversion loss. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:18-21 [Conf]
  30. Hannu Tenhunen, Dinesh Pamunuwa
    On dynamic delay and repeater insertion. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:97-100 [Conf]
  31. Bingxin Li, Hannu Tenhunen
    A structure of cascading multi-bit modulators without dynamic element matching or digital correction. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:711-714 [Conf]
  32. Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
    Optimising bandwidth over deep sub-micron interconnect. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:193-196 [Conf]
  33. Tuomas Valtonen, Tero Nurmi, Jouni Isoaho, Hannu Tenhunen
    Interconnection of autonomous error-tolerant cells. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:473-476 [Conf]
  34. Pasi Liljeberg, Imed Ben Dhaou, Juha Plosila, Jouni Isoaho, Hannu Tenhunen
    Interconnect peak current reduction for wavelet array processor using self-timed signaling. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:485-488 [Conf]
  35. Imed Ben Dhaou, Elena Dubrova, Hannu Tenhunen
    Power Efficient Inter-Module Communication for Digit-Serial DSP Architectures in Deep-Submicron Technology. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2001, pp:61-66 [Conf]
  36. Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi
    Energy Efficient Signaling in Deep Submicron CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:319-324 [Conf]
  37. Dinesh Pamunuwa, Hannu Tenhunen
    On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:240-245 [Conf]
  38. Meigen Shen, Li-Rong Zheng, Hannu Tenhunen
    Robustness Enhancement through Chip-Package Co-Design for High-Speed Electronics. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:184-189 [Conf]
  39. Meigen Shen, Li-Rong Zheng, Esa Tjukanoff, Jouni Isoaho, Hannu Tenhunen
    Concurrent Chip Package Design for Global Clock Distribution Network Using Standing Wave Approach. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:573-578 [Conf]
  40. Ana Rusu, Mohammed Ismail, Hannu Tenhunen
    A Modified Cascaded Sigma-Delta Modulator with Improved Linearity. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:77-82 [Conf]
  41. Adam Strak, Hannu Tenhunen
    Suppression of Jitter Effects in A/D Converters through Sigma-Delta Sampling. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:121-126 [Conf]
  42. Peeter Ellervee, Hannu Tenhunen
    Digital Hardware Organization Course for SoC Program. [Citation Graph (0, 0)][DBLP]
    MSE, 2001, pp:26-27 [Conf]
  43. Peter Nilsson, Petru Eles, Hannu Tenhunen
    SOCWARE: A New Swedish Design Cluster for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    MSE, 2001, pp:44-45 [Conf]
  44. Jari Nurmi, Jan Madsen, Erwin Ofner, Jouni Isoaho, Hannu Tenhunen
    The SoC-Mobinet Model in System-on-Chip Education. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:71-72 [Conf]
  45. Hannu Tenhunen, Elena Dubrova
    SoC Masters: An International M.Sc. Program in System-on-Chip Design at KTH. [Citation Graph (0, 0)][DBLP]
    MSE, 2001, pp:64-66 [Conf]
  46. Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
    Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:277-285 [Conf]
  47. Ana Rusu, Alexei Borodenkov, Mohammed Ismail, Hannu Tenhunen
    Design of a Power/Performance Efficient Single-Loop Sigma-Delta Modulator for Wireless Receivers. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:564-573 [Conf]
  48. Imed Ben Dhaou, Hannu Tenhunen
    Energy efficient high-speed on-chip signaling in deep-submicron CMOS technology. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:69-76 [Conf]
  49. Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
    Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:113-120 [Conf]
  50. Jian Liu, Meigen Shen, Li-Rong Zheng, Hannu Tenhunen
    System level interconnect design for network-on-chip using interconnect IPs. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:117-124 [Conf]
  51. Dinesh Pamunuwa, Hannu Tenhunen
    Repeater Insertion To Minimise Delay In Coupled Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:513-517 [Conf]
  52. Bengt Svantesson, Ahmed Hemani, Peeter Ellervee, Adam Postula, Johnny Öberg, Axel Jantsch, Hannu Tenhunen
    A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:23-28 [Conf]
  53. Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
    Delay-Balanced Smart Repeaters for On-Chip Global Signaling. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:308-313 [Conf]
  54. Ahmed Amine Jerraya, Hannu Tenhunen, Wayne Wolf
    Guest Editors' Introduction: Multiprocessor Systems-on-Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2005, v:38, n:7, pp:36-40 [Journal]
  55. Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen
    A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:38, n:1, pp:3-17 [Journal]
  56. Jian Liu, Li-Rong Zheng, Hannu Tenhunen
    Interconnect intellectual property for Network-on-Chip (NoC). [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:2-3, pp:65-79 [Journal]
  57. Axel Jantsch, Johnny Öberg, Hannu Tenhunen
    Special issue on networks on chip. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:2-3, pp:61-63 [Journal]
  58. Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen
    Modeling delay and noise in arbitrarily coupled RC trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1725-1739 [Journal]
  59. Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen
    Analytical model for crosstalk and intersymbol interference in point-to-point buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1400-1410 [Journal]
  60. Imed Ben Dhaou, Hannu Tenhunen
    Efficient library characterization for high-level power estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:657-661 [Journal]
  61. Meigen Shen, Jian Liu, Li-Rong Zheng, Esa Tjukanoff, Hannu Tenhunen
    Robustness enhancement through chip-package co-design for high-speed electronics. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:9, pp:846-855 [Journal]
  62. Dragos Truscan, Tiberiu Seceleanu, Hannu Tenhunen, Johan Lilius
    Towards a Design Methodology for Multiprocessor Platforms. [Citation Graph (0, 0)][DBLP]
    COMPSAC (1), 2007, pp:575-578 [Conf]
  63. Majid Baghaei Nejad, Zhuo Zou, Hannu Tenhunen, Li-Rong Zheng
    A Novel Passive Tag with Asymmetric Wireless Link for RFID and WSN Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1593-1596 [Conf]
  64. Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
    Maximizing throughput over parallel wire structures in the deep submicrometer regime. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:224-243 [Journal]

  65. Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication. [Citation Graph (, )][DBLP]

  66. Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs. [Citation Graph (, )][DBLP]

  67. On Analysis and Synthesis of (n, k)-Non-Linear Feedback Shift Registers. [Citation Graph (, )][DBLP]

  68. An efficent dynamic multicast routing protocol for distributing traffic in NOCs. [Citation Graph (, )][DBLP]

  69. On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits. [Citation Graph (, )][DBLP]

  70. Novel Agent-Based Management for Fault-Tolerance in Network-on-Chip. [Citation Graph (, )][DBLP]

  71. An Adaptive Unicast/Multicast Routing Algorithm for MPSoCs. [Citation Graph (, )][DBLP]

  72. Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks. [Citation Graph (, )][DBLP]

  73. A Model-Based Design Process for the SegBus Distributed Architecture. [Citation Graph (, )][DBLP]

  74. An Emulation Solution for the SegBus Platform. [Citation Graph (, )][DBLP]

  75. Power and Area Efficient Design of Network-on-Chip Router through Utilization of Idle Buffers. [Citation Graph (, )][DBLP]

  76. Agent-Based Reconfigurability for Fault-Tolerance in Network-on-Chip. [Citation Graph (, )][DBLP]

  77. Hardware/software partitioning and minimizing memory interface traffic. [Citation Graph (, )][DBLP]

  78. Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. [Citation Graph (, )][DBLP]

  79. A concurrent multi-band LNA for multi-standard radios. [Citation Graph (, )][DBLP]

  80. Explorations of Honeycomb Topologies for Network-on-Chip. [Citation Graph (, )][DBLP]

  81. HAMUM - A Novel Routing Protocol for Unicast and Multicast Traffic in MPSoCs. [Citation Graph (, )][DBLP]

  82. A High-Performance Network Interface Architecture for NoCs Using Reorder Buffer Sharing. [Citation Graph (, )][DBLP]

  83. Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation. [Citation Graph (, )][DBLP]

  84. Scalability of network-on-chip communication architecture for 3-D meshes. [Citation Graph (, )][DBLP]

  85. A Low-Latency and Memory-Efficient On-chip Network. [Citation Graph (, )][DBLP]

  86. An ASIC Solution for Intelligent Electrodes and Active-Cable used in a Wearable ECG Monitoring System. [Citation Graph (, )][DBLP]

  87. Application development flow for on-chip distributed architectures. [Citation Graph (, )][DBLP]

  88. 3-D memory organization and performance analysis for multi-processor network-on-chip architecture. [Citation Graph (, )][DBLP]

  89. Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. [Citation Graph (, )][DBLP]

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