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Li-Rong Zheng :
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Yuechao Niu , Majid Baghaei Nejad , Hannu Tenhunen , Li-Rong Zheng Design of a Digital Baseband Processor for UWB Transceiver on RFID Tag. [Citation Graph (0, 0)][DBLP ] AINA Workshops (2), 2007, pp:358-361 [Conf ] Li-Rong Zheng , Hannu Tenhunen Noise Margin Constraints for Interconnectivity in Deep Submicron Low Power and Mixed-Signal VLSI Circuits. [Citation Graph (0, 0)][DBLP ] ARVLSI, 1999, pp:123-136 [Conf ] Xinzhong Duo , Li-Rong Zheng , Hannu Tenhunen RF robustness enhancement through statistical analysis of chip package co-design. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2004, pp:988-991 [Conf ] Jian Liu , Li-Rong Zheng , Dinesh Pamunuwa , Hannu Tenhunen A global wire planning scheme for Network-on-Chip. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2003, pp:892-895 [Conf ] Wim Michielsen , Li-Rong Zheng , Hannu Tenhunen Analysis and design of a double tuned Clapp oscillator for multi-band multi-standard radio. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2003, pp:681-684 [Conf ] Meigen Shen , Li-Rong Zheng , Hannu Tenhunen Case study of cost and performance trade-off analysis for mixed-signal integration in system-on-chip. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2003, pp:585-588 [Conf ] Meigen Shen , Li-Rong Zheng , Esa Tjukanoff , Jouni Isoaho , Hannu Tenhunen Case study of interconnect analysis for standing wave oscillator design. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2005, pp:456-459 [Conf ] Li-Rong Zheng , Hannu Tenhunen Effective power and ground distribution scheme for deep submicron high speed VLSI circuits. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 1999, pp:537-540 [Conf ] Dinesh Pamunuwa , Li-Rong Zheng , Hannu Tenhunen Optimising bandwidth over deep sub-micron interconnect. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2002, pp:193-196 [Conf ] Meigen Shen , Li-Rong Zheng , Hannu Tenhunen Robustness Enhancement through Chip-Package Co-Design for High-Speed Electronics. [Citation Graph (0, 0)][DBLP ] ISQED, 2004, pp:184-189 [Conf ] Meigen Shen , Li-Rong Zheng , Esa Tjukanoff , Jouni Isoaho , Hannu Tenhunen Concurrent Chip Package Design for Global Clock Distribution Network Using Standing Wave Approach. [Citation Graph (0, 0)][DBLP ] ISQED, 2005, pp:573-578 [Conf ] Roshan Weerasekera , Li-Rong Zheng , Dinesh Pamunuwa , Hannu Tenhunen Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. [Citation Graph (0, 0)][DBLP ] PATMOS, 2005, pp:277-285 [Conf ] Roshan Weerasekera , Dinesh Pamunuwa , Li-Rong Zheng , Hannu Tenhunen Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. [Citation Graph (0, 0)][DBLP ] SLIP, 2006, pp:113-120 [Conf ] Jian Liu , Meigen Shen , Li-Rong Zheng , Hannu Tenhunen System level interconnect design for network-on-chip using interconnect IPs. [Citation Graph (0, 0)][DBLP ] SLIP, 2003, pp:117-124 [Conf ] Dinesh Pamunuwa , Johnny Öberg , Li-Rong Zheng , Mikael Millberg , Axel Jantsch Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:362-0 [Conf ] Roshan Weerasekera , Dinesh Pamunuwa , Li-Rong Zheng , Hannu Tenhunen Delay-Balanced Smart Repeaters for On-Chip Global Signaling. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2007, pp:308-313 [Conf ] Dinesh Pamunuwa , Johnny Öberg , Li-Rong Zheng , Mikael Millberg , Axel Jantsch , Hannu Tenhunen A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. [Citation Graph (0, 0)][DBLP ] Integration, 2004, v:38, n:1, pp:3-17 [Journal ] Jian Liu , Li-Rong Zheng , Hannu Tenhunen Interconnect intellectual property for Network-on-Chip (NoC). [Citation Graph (0, 0)][DBLP ] Journal of Systems Architecture, 2004, v:50, n:2-3, pp:65-79 [Journal ] Li-Rong Zheng , Johan Liu System-on-package: a broad perspective from system design to technology development. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2003, v:43, n:8, pp:1339-1348 [Journal ] Meigen Shen , Jian Liu , Li-Rong Zheng , Esa Tjukanoff , Hannu Tenhunen Robustness enhancement through chip-package co-design for high-speed electronics. [Citation Graph (0, 0)][DBLP ] Microelectronics Journal, 2005, v:36, n:9, pp:846-855 [Journal ] Majid Baghaei Nejad , Zhuo Zou , Hannu Tenhunen , Li-Rong Zheng A Novel Passive Tag with Asymmetric Wireless Link for RFID and WSN Applications. [Citation Graph (0, 0)][DBLP ] ISCAS, 2007, pp:1593-1596 [Conf ] Majid Baghaei Nejad , Li-Rong Zheng An innovative receiver architecture for autonomous detection of ultra-wideband signals. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Dinesh Pamunuwa , Li-Rong Zheng , Hannu Tenhunen Maximizing throughput over parallel wire structures in the deep submicrometer regime. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:224-243 [Journal ] Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. [Citation Graph (, )][DBLP ] A concurrent multi-band LNA for multi-standard radios. [Citation Graph (, )][DBLP ] Design and implementation of a fully reconfigurable chipless RFID tag using Inkjet printing technology. [Citation Graph (, )][DBLP ] Digital calibration of gain and linearity in a CMOS RF mixer. [Citation Graph (, )][DBLP ] Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks. [Citation Graph (, )][DBLP ] An ASIC Solution for Intelligent Electrodes and Active-Cable used in a Wearable ECG Monitoring System. [Citation Graph (, )][DBLP ] Traffic Splitting with Network Calculus for Mesh Sensor Networks. [Citation Graph (, )][DBLP ] Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. [Citation Graph (, )][DBLP ] Search in 0.003secs, Finished in 0.298secs