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Sudarshan Bahukudumbi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sudarshan Bahukudumbi, Krishna Bharath
    A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:804-807 [Conf]
  2. Sudarshan Bahukudumbi, Krishnendu Chakrabarty
    Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:459-464 [Conf]
  3. Sudarshan Bahukudumbi, Krishnendu Chakrabarty
    Wafer-Level Modular Testing of Core-Based SoCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1144-1154 [Journal]

  4. AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs. [Citation Graph (, )][DBLP]


  5. Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs. [Citation Graph (, )][DBLP]


  6. Test-Pattern Ordering for Wafer-Level Test-During-Burn-In. [Citation Graph (, )][DBLP]


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