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M. Jagadesh Kumar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Anurag Chaudhry, M. Jagadesh Kumar
    Exploring the Novel Characteristics of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET using Two-Dimensional Numerical Simulation Studies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:662-665 [Conf]
  2. M. Jagadesh Kumar, Ali A. Orouji
    Phase Change Memory Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:108-112 [Conf]
  3. M. Jagadesh Kumar, Vinod Parihar
    A New Surface Accumulation Layer Transistor(SALTran) Concept for Current Gain Enhancement in Bipolar Transistors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:827-831 [Conf]
  4. M. Jagadesh Kumar, D. Venkateshrao
    A New Lateral SiGe-Base PNM Schottky Collector Bipolar Transistor on SOI for Non-saturating VLSI Logic Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:489-492 [Conf]
  5. M. Jagadesh Kumar, Vivek Venkataraman, Susheel Nawal
    Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:189-194 [Conf]
  6. M. Jagadesh Kumar, C. Linga Reddy
    2D-simulation and analysis of lateral SiC N-emitter SiGe P-base Schottky metal-collector (NPM) HBT on SOI. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:7, pp:1145-1149 [Journal]
  7. G. Venkateshwar Reddy, M. Jagadesh Kumar
    Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2004, v:35, n:9, pp:761-765 [Journal]

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