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V. Ramgopal Rao: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Abhisek Dixit, V. Ramgopal Rao
    A Novel Dynamic Threshold Operation Using Electrically Induced Junction MOSFET in the Deep Sub-micrometer CMOS Regime. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:499-503 [Conf]
  2. Najeebuddin Hakim, V. Ramgopal Rao, J. Vasi
    Small Signal Characteristics of Thin Film Single Halo SOI MOSFET for Mixed Mode Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:110-115 [Conf]
  3. D. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao
    Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:128-0 [Conf]
  4. Nihar R. Mohapatra, A. Dutta, Madhav P. Desai, V. Ramgopal Rao
    Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:479-0 [Conf]
  5. Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao
    Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:99-104 [Conf]
  6. K. Narasimhulu, Siva Narendra, V. Ramgopal Rao
    The Influence of Process Variations on the Halo MOSFETs and its Implications on the Analog Circuit performance. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:545-550 [Conf]
  7. K. Narasimhulu, V. Ramgopal Rao
    Embedded Tutorial: Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:45-50 [Conf]
  8. G. Shrivastav, S. Mahapatra, V. Ramgopal Rao, J. Vasi, K. G. Anil, C. Fink, Walter Hansch, I. Eisele
    erformance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:475-478 [Conf]
  9. Nihar R. Mohapatra, A. Dutta, G. Sridhar, Madhav P. Desai, V. Ramgopal Rao
    Sub-100 nm CMOS circuit performance with high-K gate dielectrics. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:7, pp:1045-1048 [Journal]

  10. Automated design and optimization of circuits in emerging technologies. [Citation Graph (, )][DBLP]


  11. Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework. [Citation Graph (, )][DBLP]


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