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Publications of Author

1. Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran
   Rapid Embedded Hardware/Software System Generation. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2005, pp:111-116 [Conf]
   
2. Jorgen Peddersen, Sri Parameswaran
   Energy Driven Application SelfAdaptation. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2007, pp:385-390 [Conf]
   
3. 
   CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time. [Citation Graph (, )][DBLP]
   
   
4. 
   LOP: a novel SRAM-based architecture for low power and high throughput packet classification. [Citation Graph (, )][DBLP]
   
   
5. 
   SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. [Citation Graph (, )][DBLP]
   
   
6. 
   DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. [Citation Graph (, )][DBLP]
   
   
7. 
   Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm. [Citation Graph (, )][DBLP]
   
   
8. 
   LOP_RE: Range encoding for low power packet classification. [Citation Graph (, )][DBLP]
   
   
9. 
   ACS: Automatic Converter Synthesis for SoC Bus Protocols. [Citation Graph (, )][DBLP]
   
   
10. 
    Low-Impact Processor for Dynamic Runtime Power Management. [Citation Graph (, )][DBLP]