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Chia-Fang Lee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jin-Tai Yan, Chia-Fang Lee, Yen-Hsiang Chen
    Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:147-152 [Conf]
  2. Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee
    Timing-constrained yield-driven wire sizing for critical area minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  3. Jin-Tai Yan, Yen-Hsiang Chen, Chia-Fang Lee, Ming-Ching Huang
    Multilevel timing-constrained full-chip routing in hierarchical quad-grid model. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

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