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Lizy K. John: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jiajin Tu, Jian Chen, Lizy K. John
    Hardware Efficient Piecewise Linear Branch Predictor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:673-678 [Conf]
  2. Ajay Joshi, Yue Luo, Lizy K. John
    Applying Statistical Sampling for Fast and Efficient Simulation of Commercial Workloads. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:11, pp:1520-1533 [Journal]

  3. Loop-Aware Instruction Scheduling with Dynamic Contention Tracking for Tiled Dataflow Architectures. [Citation Graph (, )][DBLP]

  4. Simulation points for SPEC CPU 2006. [Citation Graph (, )][DBLP]

  5. Bank-aware Dynamic Cache Partitioning for Multicore Architectures. [Citation Graph (, )][DBLP]

  6. Analysis of dynamic power management on multi-core processors. [Citation Graph (, )][DBLP]

  7. The virtual write queue: coordinating DRAM and last-level cache policies. [Citation Graph (, )][DBLP]

  8. Automatic testcase synthesis and performance model validation for high performance PowerPC processors. [Citation Graph (, )][DBLP]

  9. Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events. [Citation Graph (, )][DBLP]

  10. Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads. [Citation Graph (, )][DBLP]

  11. TSS: Applying two-stage sampling in micro-architecture simulations. [Citation Graph (, )][DBLP]

  12. CantorSim: Simplifying Acceleration of Micro-architecture Simulations. [Citation Graph (, )][DBLP]

  13. Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education. [Citation Graph (, )][DBLP]

  14. OS-aware tuning: improving instruction cache energy efficiency on system workloads. [Citation Graph (, )][DBLP]

  15. A Tale of Two Processors: Revisiting the RISC-CISC Debate. [Citation Graph (, )][DBLP]

  16. Generation, Validation and Analysis of SPEC CPU2006 Simulation Points Based on Branch, Memory and TLB Characteristics. [Citation Graph (, )][DBLP]

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