The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Peter M. Maurer: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Peter M. Maurer
    The FHDL macro processor. [Citation Graph (0, 0)][DBLP]
    ACM Southeast Regional Conference, 1990, pp:10-17 [Conf]
  2. Peter M. Maurer, Craig D. Morency
    The FHDL PLA tools. [Citation Graph (0, 0)][DBLP]
    ACM Southeast Regional Conference, 1990, pp:3-9 [Conf]
  3. Peter M. Maurer, Craig D. Morency
    The FHDL ROM tools. [Citation Graph (0, 0)][DBLP]
    ACM Southeast Regional Conference, 1990, pp:18-24 [Conf]
  4. Yun Sik Lee, Peter M. Maurer
    Two New Techniques for Compiled Multi-Delay Logic Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:420-423 [Conf]
  5. Peter M. Maurer, Zhicheng Wang
    Techniques for Unit-Delay Compiled Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:480-484 [Conf]
  6. Zhicheng Wang, Peter M. Maurer
    Scheduling High-Level Blocks for Functional Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:87-90 [Conf]
  7. Zhicheng Wang, Peter M. Maurer
    LECSIM: A Levelized Event Driven Compiled Logic Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:491-496 [Conf]
  8. Peter M. Maurer
    Logic Simulation Using Networks of State Machines. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:674-678 [Conf]
  9. Peter M. Maurer
    Using conjugate symmetries to enhance gate-level simulations. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:638-643 [Conf]
  10. Peter M. Maurer, William J. Schilp
    Software Bit-Slicing: A Technique for Improving Simulation Performance. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:786-787 [Conf]
  11. William B. Poucher, Peter M. Maurer
    How to Make Program Assessment Work for You. [Citation Graph (0, 0)][DBLP]
    FECS, 2005, pp:83-87 [Conf]
  12. Yun Sik Lee, Peter M. Maurer
    Parallel multi-delay simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:759-762 [Conf]
  13. Peter M. Maurer
    Event Driven Simulation Without Loops or Conditionals. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:23-26 [Conf]
  14. Peter M. Maurer
    Optimization of the Parallel Technique for Compiled Unit-Delay Simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:70-73 [Conf]
  15. Peter M. Maurer
    The Inversion Algorithm for digital simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:258-261 [Conf]
  16. William J. Schilp, Peter M. Maurer
    Unit delay simulation with the inversion algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:412-417 [Conf]
  17. Peter M. Maurer
    Mapping the Data Flow Model of Computation into an Enhanced Von Neumann Processor. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:235-239 [Conf]
  18. Sandeep K. Kondapuram, Peter M. Maurer
    Random Characterization of Design Automation Algorithms. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:264-265 [Conf]
  19. Allen S. Parrish, Joe Hollingsworth, Peter M. Maurer, Benjamin Shults, Bruce W. Weide
    Identifying an appropriate view of software components for undergraduate education. [Citation Graph (0, 0)][DBLP]
    SIGCSE, 2001, pp:394-395 [Conf]
  20. Peter M. Maurer
    Is Compiled Simulation Really Faster than Interpreted Simulation? [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:303-306 [Conf]
  21. Peter M. Maurer
    Efficient Simulation for Hierarchical and Partitioned Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:236-241 [Conf]
  22. Peter M. Maurer, William J. Schilp
    State-Machine Based Logic Simulation Using Three Logic Values. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:430-435 [Conf]
  23. Peter M. Maurer, Arthur E. Oldehoeft
    The Use of Combinators in Translating A Purely Functional Language to Low-Level Data-Flow Graphs. [Citation Graph (0, 0)][DBLP]
    Comput. Lang., 1983, v:8, n:1, pp:27-45 [Journal]
  24. Peter M. Maurer
    Components: What If They Gave a Revolution and Nobody Came? [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2000, v:33, n:6, pp:28-34 [Journal]
  25. Peter M. Maurer
    Metamorphic Programming: Unconventional High Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:3, pp:30-38 [Journal]
  26. Peter M. Maurer
    Dynamic Functional Testing for VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1990, v:7, n:6, pp:42-49 [Journal]
  27. Peter M. Maurer
    Generating Test Data with Enhanced Context-Free Grammars. [Citation Graph (0, 0)][DBLP]
    IEEE Software, 1990, v:7, n:4, pp:50-55 [Journal]
  28. Peter M. Maurer
    The Design and Implementation of a Grammar-based Data Generator. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1992, v:22, n:3, pp:223-244 [Journal]
  29. Peter M. Maurer
    Converting command-line applications into binary components. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 2005, v:35, n:8, pp:787-797 [Journal]
  30. Yun Sik Lee, Peter M. Maurer
    Bit-parallel multidelay simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1547-1554 [Journal]
  31. Peter M. Maurer
    Efficient event-driven simulation by exploiting the output observability of gate clusters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1471-1486 [Journal]
  32. Peter M. Maurer
    Scheduling blocks of hierarchical compiled simulation of combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:184-192 [Journal]
  33. Peter M. Maurer
    Two new techniques for unit-delay compiled simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1120-1130 [Journal]
  34. Peter M. Maurer
    The shadow algorithm: a scheduling technique for both compiled and interpreted simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1411-1413 [Journal]
  35. Peter M. Maurer
    The inversion algorithm for digital simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:762-769 [Journal]
  36. Peter M. Maurer, Yun Sik Lee
    Gateways: a technique for adding event-driven behavior to compiled simulations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:338-352 [Journal]
  37. Peter M. Maurer, Alexander D. Schapira
    A logic-to-logic comparator for VLSI layout verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:897-907 [Journal]

Search in 0.003secs, Finished in 0.004secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002