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Franc Brglez: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh
    Heuristics and Experimental Design for Bigraph Crossing Number Minimization. [Citation Graph (0, 0)][DBLP]
    ALENEX, 1999, pp:74-93 [Conf]
  2. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
    Clock Period Optimization During Resource Sharing and Assignment. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:195-200 [Conf]
  3. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
    Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:491-496 [Conf]
  4. Franc Brglez, Hemang Lavana
    A Universal Client for Distributed Networked Design and Computing. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:401-406 [Conf]
  5. Sujit Dey, Franc Brglez, Gershon Kedem
    Corolla Based Circuit Partitioning and Resynthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:607-612 [Conf]
  6. Roman Kuznar, Franc Brglez, Krzysztof Kozminski
    Cost Minimization of Partitions into Multiple Devices. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:315-320 [Conf]
  7. Roman Kuznar, Franc Brglez, Baldomir Zajc
    Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:238-243 [Conf]
  8. Hemang Lavana, Amit Khetawat, Franc Brglez, Krzysztof Kozminski
    Executable Workflows: A Paradigm for Collaborative Design on the Internet. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:553-558 [Conf]
  9. Xiao Yu Li, Matthias F. M. Stallmann, Franc Brglez
    Effective bounding techniques for solving unate and binate covering problems. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:385-390 [Conf]
  10. Ulf Schlichtmann, Franc Brglez, Michael Hermann
    Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:374-379 [Conf]
  11. Michael H. Schultz, Franc Brglez
    Accelerated Transition Fault Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:237-243 [Conf]
  12. Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III
    Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:656-663 [Conf]
  13. Bernhard Rohfleisch, Franc Brglez
    Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:87-93 [Conf]
  14. Andrej Zemva, Franc Brglez, Krzysztof Kozminski, Baldomir Zajc
    A Functionality Fault Model: Feasibility and Applications. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:152-158 [Conf]
  15. Justin E. Harlow III, Franc Brglez
    Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1998, pp:64-81 [Conf]
  16. Hemang Lavana, Amit Khetawat, Franc Brglez
    Internet-based workflows: a paradigm for dynamically reconfigurable desktop environments. [Citation Graph (0, 0)][DBLP]
    GROUP, 1997, pp:204-213 [Conf]
  17. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
    Provably correct high-level timing analysis without path sensitization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:736-742 [Conf]
  18. Justin E. Harlow III, Franc Brglez
    Design of experiments in BDD variable ordering: lessons learned. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:646-652 [Conf]
  19. Roman Kuznar, Franc Brglez
    PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:644-649 [Conf]
  20. Sujit Dey, Franc Brglez, Gershon Kedem
    Partitioning Sequential Circuits for Logic Optimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:70-76 [Conf]
  21. Hemang Lavana, Franc Brglez, Robert B. Reese, Gangadhar Konduri, Anantha Chandrakasan
    OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:567-570 [Conf]
  22. Debabrata Ghosh, Franc Brglez
    Equivalence classes of circuit mutants for experimental design. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:432-435 [Conf]
  23. Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh
    Evaluating iterative improvement heuristics for bigraph crossing minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:444-447 [Conf]
  24. Justin E. Harlow III, Franc Brglez
    Mirror, mirror, on the wall...is the new release any different at all? [BDDs]. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:452-455 [Conf]
  25. Franc Brglez, Rolf Drechsler
    Design of experiments in CAD: context and new data sets for ISCAS'99. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:424-427 [Conf]
  26. Hemang Lavana, Franc Brglez, Robert B. Reese
    User-configurable experimental design flows on the web: the ISCAS'99 experiments. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:440-443 [Conf]
  27. Nevin Kapur, Debabrata Ghosh, Franc Brglez
    Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:136-143 [Conf]
  28. John D. Calhoun, Franc Brglez
    A Framework and Method for Hierarchical Test Generation. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:480-490 [Conf]
  29. Franc Brglez
    Digital Signal Processing Considerations in Filter-Codec Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1981, pp:193-202 [Conf]
  30. Franc Brglez
    A Fast Fault Grader: Analysis and Applications. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:785-794 [Conf]
  31. Franc Brglez
    Fault Coverage Tools: Case Studies. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:797-800 [Conf]
  32. Franc Brglez, Gershon Kedem, Clay Gloster
    Hardware-Based Weighted Random Pattern Generation for Boundary Scan. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:264-274 [Conf]
  33. Franc Brglez, Philip Pownall, Robert Hum
    Applications of Testability Analysis: From ATPG to Critical Delay Path Tracing. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:705-712 [Conf]
  34. Clay Gloster, Franc Brglez
    Boundary Scan with Cellular-Based Built-In Self-Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:138-145 [Conf]
  35. Matthew Melton, Franc Brglez
    Automatic Pattern Generation for Diagnosis of Wiring Interconnect Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:389-398 [Conf]
  36. Xiao Yu Li, Matthias F. M. Stallmann, Franc Brglez
    A Local Search SAT Solver Using an Effective Switching Strategy and an Efficient Unit Propagation. [Citation Graph (0, 0)][DBLP]
    SAT, 2003, pp:53-68 [Conf]
  37. Sujit Dey, Franc Brglez, Gershon Kedem
    Identification and Resynthesis of Pipelines in Sequential Networks. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:439-449 [Conf]
  38. Andrej Zemva, Franc Brglez
    Detectable perturbations: a paradigm for technology-specific multi-fault test generation. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:350-357 [Conf]
  39. Franc Brglez, Xiao Yu Li, Matthias F. M. Stallmann
    On SAT instance classes and a method for reliable performance experiments with SAT solvers. [Citation Graph (0, 0)][DBLP]
    Ann. Math. Artif. Intell., 2005, v:43, n:1, pp:1-34 [Journal]
  40. Franc Brglez
    The Scientific Method and Design and Test. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:3, pp:142-144 [Journal]
  41. Franc Brglez
    A D&T Special Report on ACM/SIGDA Design Automation Benchmarks: Catalyst or Anathema? [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:3, pp:87-91 [Journal]
  42. Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh
    Heuristics, Experimental Subjects, and Treatment Evaluation in Bigraph Crossing Minimization. [Citation Graph (0, 0)][DBLP]
    ACM Journal of Experimental Algorithms, 2001, v:6, n:, pp:8- [Journal]
  43. Justin E. Harlow III, Franc Brglez
    Design of experiments and evaluation of BDD ordering heuristics. [Citation Graph (0, 0)][DBLP]
    STTT, 2001, v:3, n:2, pp:193-206 [Journal]
  44. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
    Fast true delay estimation during high level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1088-1105 [Journal]
  45. John D. Calhoun, Franc Brglez
    A framework and method for hierarchical test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:1, pp:45-67 [Journal]
  46. Robert Lisanke, Franc Brglez, Aart J. de Geus, David Gregory
    Testability-Driven Random Test-Pattern Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1082-1087 [Journal]
  47. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
    Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:285-307 [Journal]
  48. Subhrajit Bhattacharya, Franc Brglez, Sujit Dey
    Transformations and resynthesis for testability of RT-level control-data path specifications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:3, pp:304-318 [Journal]

  49. Partial scan selection for user-specified fault coverage. [Citation Graph (, )][DBLP]


  50. A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions. [Citation Graph (, )][DBLP]


  51. Performance testing of combinatorial solvers with isomorph class instances. [Citation Graph (, )][DBLP]


  52. High-contrast algorithm behavior: observation, hypothesis, and experimental design. [Citation Graph (, )][DBLP]


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