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Debabrata Ghosh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh
    Heuristics and Experimental Design for Bigraph Crossing Number Minimization. [Citation Graph (0, 0)][DBLP]
    ALENEX, 1999, pp:74-93 [Conf]
  2. Debabrata Ghosh, S. K. Nandy, P. Sadayappan, K. Parthasarathy
    Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:303-307 [Conf]
  3. Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III
    Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:656-663 [Conf]
  4. Debabrata Ghosh, S. K. Nandy
    A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:198-201 [Conf]
  5. Debabrata Ghosh, Franc Brglez
    Equivalence classes of circuit mutants for experimental design. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:432-435 [Conf]
  6. Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh
    Evaluating iterative improvement heuristics for bigraph crossing minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:444-447 [Conf]
  7. Nevin Kapur, Debabrata Ghosh, Franc Brglez
    Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:136-143 [Conf]
  8. Debabrata Ghosh, Soumitra Kumar Nandy
    Wave pipelined architecture folding: a method to achieve low power and low area. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:184-0 [Conf]
  9. Debabrata Ghosh, S. K. Nandy, K. Parthasarathy
    TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:77-82 [Conf]
  10. Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan
    NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:341-346 [Conf]
  11. Debabrata Ghosh, Shamik Sural, S. K. Nandy
    A 600MHz Half-Bit Level Pipelined Multiplier Macrocell. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:95-100 [Conf]
  12. Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh
    Heuristics, Experimental Subjects, and Treatment Evaluation in Bigraph Crossing Minimization. [Citation Graph (0, 0)][DBLP]
    ACM Journal of Experimental Algorithms, 2001, v:6, n:, pp:8- [Journal]
  13. Debabrata Ghosh, S. K. Nandy
    Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:36-48 [Journal]

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