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Title:
Author:
Andrew B. Kahng: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning. [Citation Graph (0, 0)][DBLP]
    ALENEX, 1999, pp:177-193 [Conf]
  2. Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky
    Monte-Carlo algorithms for layout density control. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:523-528 [Conf]
  3. Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky
    Hierarchical dummy fill for process uniformity. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:139-144 [Conf]
  4. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Improved algorithms for hypergraph bipartitioning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:661-666 [Conf]
  5. Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky
    Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:580-591 [Conf]
  6. Ross Baldick, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov
    Function Smoothing with Applications to VLSI Layout. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:225-0 [Conf]
  7. Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang
    Optimal planning for mesh-based power distribution. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:444-449 [Conf]
  8. Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt
    Toward better wireload models in the presence of obstacles. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:527-532 [Conf]
  9. C. K. Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen
    Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:- [Conf]
  10. Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky
    Provably good global buffering by multi-terminal multicommodity flow approximation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:120-125 [Conf]
  11. Puneet Gupta, Andrew B. Kahng, Chul-Hong Park
    Detailed placement for improved depth of focus and CD control. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:343-348 [Conf]
  12. Andrew B. Kahng
    Design technology productivity in the DSM era (invited talk). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:443-448 [Conf]
  13. Andrew B. Kahng, Sherief Reda
    Combinatorial group testing methods for the BIST diagnosis problem. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:113-116 [Conf]
  14. Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky
    New Multilevel and Hierarchical Algorithms for Layout Density Control. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:221-224 [Conf]
  15. Andrew B. Kahng, Paul Tucker, Alexander Zelikovsky
    Optimization of Linear Placements for Wirelength Minimization with Free Sites. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:241-244 [Conf]
  16. Andrew B. Kahng, Shailesh Vaya, Alexander Zelikovsky
    New graph bipartizations for double-exposure, bright field alternating phase-shift mask layout. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:133-138 [Conf]
  17. Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori
    Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:267-268 [Conf]
  18. Charles J. Alpert, Andrew B. Kahng
    Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:743-748 [Conf]
  19. Charles J. Alpert, Andrew B. Kahng
    Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:652-657 [Conf]
  20. Dominic A. Antonelli, Danny Z. Chen, Timothy J. Dysart, Xiaobo Sharon Hu, Andrew B. Kahng, Peter M. Kogge, Richard C. Murphy, Michael T. Niemier
    Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:363-368 [Conf]
  21. Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang
    Timing-driven Steiner trees are (practically) free. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:389-392 [Conf]
  22. Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng
    Multilevel Circuit Partitioning. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:530-533 [Conf]
  23. Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins
    Rectilinear Steiner Trees with Minimum Elmore Delay. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:381-386 [Conf]
  24. Kenneth D. Boese, Andrew B. Kahng, Gabriel Robins
    High-Performance Routing Trees With Identified Critical Sinks. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:182-187 [Conf]
  25. Andrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farinaz Koushanfar, Hua Lu, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester
    GTX: the MARCO GSRC technology extrapolation system. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:693-698 [Conf]
  26. Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong
    Effective Iterative Techniques for Fingerprinting Design IP. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:843-848 [Conf]
  27. Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov
    Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:349-354 [Conf]
  28. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Can recursive bisection alone produce routable placements? [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:477-482 [Conf]
  29. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Hypergraph Partitioning with Fixed Vertices. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:355-359 [Conf]
  30. Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang
    Toward a methodology for manufacturability-driven design rule exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:311-316 [Conf]
  31. Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu
    An algebraic multigrid solver for analytical placement with layout based clustering. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:794-799 [Conf]
  32. Yu Chen, Puneet Gupta, Andrew B. Kahng
    Performance-impact limited area fill synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:22-27 [Conf]
  33. Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky
    Practical iterated fill synthesis for CMP uniformity. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:671-674 [Conf]
  34. Yongseok Cheon, Pei-Hsin Ho, Andrew B. Kahng, Sherief Reda, Qinke Wang
    Power-aware placement. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:795-800 [Conf]
  35. Jason Cong, Lars W. Hagen, Andrew B. Kahng
    Net Partitions Yield Better Module Partitions. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:47-52 [Conf]
  36. Jason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve H.-C. Yen
    Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:627-632 [Conf]
  37. Stephen Fenstermaker, David George, Andrew B. Kahng, Stefanus Mantik, Bart Thielges
    METRICS: a system architecture for design process optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:705-710 [Conf]
  38. Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester
    Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:365-368 [Conf]
  39. Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester
    Selective gate-length biasing for cost-effective runtime leakage control. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:327-330 [Conf]
  40. Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang
    A cost-driven lithographic correction methodology based on off-the-shelf sizing tools. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:16-21 [Conf]
  41. Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng
    Quantified Suboptimality of VLSI Layout Heuristics. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:216-221 [Conf]
  42. Dennis J.-H. Huang, Andrew B. Kahng, Chung-Wen Albert Tsao
    On the Bounded-Skew Clock and Steiner Routing Problems. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:508-513 [Conf]
  43. Andrew B. Kahng
    CAD challenges for leading-edge multimedia designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:372- [Conf]
  44. Andrew B. Kahng
    Fast Hypergraph Partition. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:762-766 [Conf]
  45. Andrew B. Kahng, Shekhar Borkar, John Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf
    Nanometer design: place your bets. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:546-547 [Conf]
  46. Andrew B. Kahng, Ronald Collett, Patrick Groeneveld, Lavi Lev, Nancy Nettleton, Paul K. Rodman, Lambert van den Hoven
    Tools or users: which is the bigger bottleneck? [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:76-77 [Conf]
  47. Andrew B. Kahng, Jason Cong, Gabriel Robins
    High-Performance Clock Routing Based on Recursive Geometric Aatching. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:322-327 [Conf]
  48. Andrew B. Kahng, John Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe
    Watermarking Techniques for Intellectual Property Protection. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:776-781 [Conf]
  49. Andrew B. Kahng, Sudhakar Muddu
    Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:563-569 [Conf]
  50. Andrew B. Kahng, Sudhakar Muddu
    Analysis of RC Interconnections Under Ramp Input. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:533-538 [Conf]
  51. Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe
    Robust IP Watermarking Methodologies for Physical Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:782-787 [Conf]
  52. Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
    On switch factor based analysis of coupled RC interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:79-84 [Conf]
  53. Andrew B. Kahng, Y. C. Pati
    Subwavelength Lithography and Its Potential Impact on Design and EDA. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:799-804 [Conf]
  54. Andrew B. Kahng, Y. C. Pati, Warren Grobman, Robert Pack, Lance A. Glasser
    Subwavelength Lithography: How Will It Affect Your Design Flow? (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:798- [Conf]
  55. Andrew B. Kahng, Sherief Reda
    Placement feedback: a concept and method for better min-cut placements. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:357-362 [Conf]
  56. Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang
    Panel: Is Nanometer Design Under Control? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:591-592 [Conf]
  57. Andrew B. Kahng, Chung-Wen Albert Tsao
    More Practical Bounded-Skew Clock Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:594-599 [Conf]
  58. Saumil Shah, Puneet Gupta, Andrew B. Kahng
    Standard cell library optimization for leakage reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:983-986 [Conf]
  59. Jennifer Smith, Tom Quan, Andrew B. Kahng
    EDA meets.COM (panel session): how E-services will change the EDA business model. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:253- [Conf]
  60. Charles Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky
    Bright-Field AAPSM Conflict Detection and Correction. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:908-913 [Conf]
  61. Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng
    Area Fill Generation With Inherent Data Volume Reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10868-10875 [Conf]
  62. Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Muddu
    A Novel Metric for Interconnect Architecture Performance. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10448-10455 [Conf]
  63. Andrew B. Kahng, Igor L. Markov, Sherief Reda
    Boosting: Min-Cut Placement with Improved Signal Delay. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1098-1103 [Conf]
  64. Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma
    Interconnect Tuning Strategies for High-Performance Ics. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:471-478 [Conf]
  65. Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang
    Lens aberration aware timing-driven placement. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:890-895 [Conf]
  66. Dennis J.-H. Huang, Andrew B. Kahng
    Multi-way System Partitioning into a Single Type or Multiple Types of FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:140-145 [Conf]
  67. Andrew B. Kahng, Bao Liu, Xu Xu
    Statistical gate delay calculation with crosstalk alignment consideration. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:223-228 [Conf]
  68. Andrew B. Kahng, Igor L. Markov, Sherief Reda
    On legalization of row-based placements. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:214-219 [Conf]
  69. Charles J. Alpert, Andrew B. Kahng
    A general framework for vertex orderings, with applications to netlist clustering. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:63-67 [Conf]
  70. Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
    Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:408-0 [Conf]
  71. Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester
    Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:56-61 [Conf]
  72. Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao
    The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:13-20 [Conf]
  73. Yu Chen, Andrew B. Kahng, Gang Qu, Alexander Zelikovsky
    The associative-skew clock routing problem. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:168-172 [Conf]
  74. Charles Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu
    Fast and efficient phase conflict detection and correction in standard-cell layouts. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:149-156 [Conf]
  75. Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao
    Bounded-skew clock and Steiner routing under Elmore delay. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:66-71 [Conf]
  76. Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky
    Provably Good Global Buffering Using an Available Buffer Block Plan. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:104-109 [Conf]
  77. Puneet Gupta, Andrew B. Kahng
    Manufacturing-Aware Physical Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:681-688 [Conf]
  78. Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma
    Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:754-759 [Conf]
  79. Lars W. Hagen, Andrew B. Kahng
    Fast Spectral Methods for Ratio Cut Partitioning and Clustering. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:10-13 [Conf]
  80. Lars W. Hagen, Andrew B. Kahng
    A new approach to effective circuit clustering. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:422-427 [Conf]
  81. Andrew B. Kahng, Darko Kirovski, Stefanus Mantik, Miodrag Potkonjak, Jennifer L. Wong
    Copy detection for intellectual property protection of VLSI designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:600-605 [Conf]
  82. Andrew B. Kahng, Bao Liu, Ion I. Mandoiu
    Non-tree routing for reliability and yield improvement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:260-266 [Conf]
  83. Andrew B. Kahng, Stefanus Mantik
    On Mismatches between Incremental Optimizers and Instance Perturbations in Physical Design Tools. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:17-21 [Conf]
  84. Andrew B. Kahng, Kei Masuko, Sudhakar Muddu
    Analytical delay models for VLSI interconnects under ramp input. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:30-36 [Conf]
  85. Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky
    Evaluation of Placement Techniques for DNA Probe Array Layout. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:262-269 [Conf]
  86. Andrew B. Kahng, Sherief Reda
    Intrinsic shortest path length: a new, accurate a priori wirelength estimator. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:173-180 [Conf]
  87. Andrew B. Kahng, Gabriel Robins
    A New Class of Steiner Trees Heuristics with Good Performance: The Iterated 1-Steiner-Approach. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:428-431 [Conf]
  88. Andrew B. Kahng, Sherief Reda, Qinke Wang
    Architecture and details of a high quality, large-scale analytical placer. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:891-898 [Conf]
  89. Andrew B. Kahng, Chung-Wen Albert Tsao
    Low-cost single-layer clock trees with exact zero Elmore delay skew. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:213-218 [Conf]
  90. Andrew B. Kahng, Qinke Wang
    An analytic placer for mixed-size placement and timing-driven placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:565-572 [Conf]
  91. Andrew B. Kahng, Puneet Sharma, Alexander Zelikovsky
    Fill for shallow trench isolation CMP. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:661-668 [Conf]
  92. Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins
    Fidelity and Near-Optimality of Elmore-Based Routing Constructions. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:81-84 [Conf]
  93. Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen
    An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:154-158 [Conf]
  94. Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, C. K. Wong
    Performance-Driven Global Routing for Cell Based ICs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:170-173 [Conf]
  95. Andrew B. Kahng
    An Effective Analog Approach to Steiner Routing. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:166-169 [Conf]
  96. Andrew B. Kahng, Bao Liu, Qinke Wang
    Supply Voltage Degradation Aware Analytical Placement. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:437-443 [Conf]
  97. Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky
    Design Flow Enhancements for DNA Arrays. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:116-0 [Conf]
  98. Andrew B. Kahng, Byung Ro Moon
    Toward More Powerful Recombinations. [Citation Graph (0, 0)][DBLP]
    ICGA, 1995, pp:96-103 [Conf]
  99. C. Bandela, Yu Chen, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky
    Auctions with Buyer Preferences. [Citation Graph (0, 0)][DBLP]
    Information Systems: The e-Business Challenge, 2002, pp:223-238 [Conf]
  100. Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh
    Minimum Density Interconneciton Trees. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1865-1868 [Conf]
  101. Charles J. Alpert, T. C. Hu, Jen-Hsin Huang, Andrew B. Kahng
    A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1869-1872 [Conf]
  102. Kenneth D. Boese, Andrew B. Kahng
    Simulated annealing of neural networks: The 'cooling' strategy reconsidered. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2572-2575 [Conf]
  103. Andrew B. Kahng, Swamy Muddu, Puneet Sharma
    Defocus-aware leakage estimation and control. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:263-268 [Conf]
  104. Andrew B. Kahng
    A roadmap and vision for physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:112-117 [Conf]
  105. Andrew B. Kahng
    Research directions for coevolution of rules and routers. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:122-125 [Conf]
  106. Andrew B. Kahng
    Futures for partitioning in physical design (tutorial). [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:190-193 [Conf]
  107. Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan
    Efficient decoupling capacitor planning via convex programming methods. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:102-107 [Conf]
  108. Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, Kenneth Yan
    Faster minimization of linear wirelength for global placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:4-11 [Conf]
  109. Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Partitioning with terminals: a "new" problem and new benchmarks. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:151-157 [Conf]
  110. Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
    Buffered Steiner trees for difficult instances. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:4-9 [Conf]
  111. Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia
    A semi-persistent clustering technique for VLSI circuit placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:200-207 [Conf]
  112. Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Huijuan Wang, Alexander Zelikovsky
    Optimal phase conflict removal for layout of dark field alternating phase shifting masks. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:121-126 [Conf]
  113. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Optimal partitioners and end-case placers for standard-cell layout. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:90-96 [Conf]
  114. Jason Cong, Andrew B. Kahng, Kwok-Shing Leung
    Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:88-95 [Conf]
  115. Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky
    On wirelength estimations for row-based placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:4-11 [Conf]
  116. Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong
    Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:78-85 [Conf]
  117. Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky
    Closing the smoothness and uniformity gap in area fill synthesis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:137-142 [Conf]
  118. Andrew B. Kahng, Sudhakar Muddu
    New efficient algorithms for computing effective capacitance. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:147-151 [Conf]
  119. Dennis J.-H. Huang, Andrew B. Kahng
    Partitioning-based standard-cell global placement with an exact objective. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:18-25 [Conf]
  120. Andrew B. Kahng
    Classical floorplanning harmful? [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:207-213 [Conf]
  121. Andrew B. Kahng, Stefanus Mantik, Igor L. Markov
    Min-max placement for large-scale timing optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:143-148 [Conf]
  122. Andrew B. Kahng, Stefanus Mantik, Dirk Stroobandt
    Requirements for models of achievable routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:4-11 [Conf]
  123. Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Xu Xu, Alexander Zelikovsky
    Multi-project reticle floorplanning and wafer dicing. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:70-77 [Conf]
  124. Andrew B. Kahng, Y. C. Pati
    Subwavelength optical lithography: challenges and impact on physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:112-119 [Conf]
  125. Andrew B. Kahng, Sherief Reda
    Evaluation of placer suboptimality via zero-change netlist transformations. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:208-215 [Conf]
  126. Andrew B. Kahng, Gabriel Robins, Anish Singh, Huijuan Wang, Alexander Zelikovsky
    Filling and slotting: analysis and algorithms. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:95-102 [Conf]
  127. Andrew B. Kahng, Sherief Reda, Qinke Wang
    APlace: a general analytic placement framework. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:233-235 [Conf]
  128. Andrew B. Kahng, Qinke Wang
    Implementation and extensibility of an analytic placer. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:18-25 [Conf]
  129. Andrew B. Kahng, Qinke Wang
    A faster implementation of APlace. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:218-220 [Conf]
  130. Andrew B. Kahng, Xu Xu
    Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:81-86 [Conf]
  131. Puneet Gupta, Andrew B. Kahng
    Quantifying Error in Dynamic Power Estimation of CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:273-278 [Conf]
  132. Puneet Gupta, Andrew B. Kahng, Stefanus Mantik
    A Proposal for Routing-Based Timing-Driven Scan Chain Ordering. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:339-343 [Conf]
  133. Puneet Gupta, Andrew B. Kahng, Puneet Sharma
    A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:421-426 [Conf]
  134. Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang
    Performance Driven OPC for Mask Cost Reduction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:270-275 [Conf]
  135. Andrew B. Kahng
    Manufacturability . [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:8- [Conf]
  136. Andrew B. Kahng, Ronald Collett, Ton. H. van de Kraats
    Design Metrics to Achieve Design Quality. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:9- [Conf]
  137. Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan
    SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:638-643 [Conf]
  138. Andrew B. Kahng, Bao Liu, Xu Xu
    Constructing Current-Based Gate Models Based on Existing Timing Library. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:37-42 [Conf]
  139. Andrew B. Kahng, Stefanus Mantik
    A System for Automatic Recording and Prediction of Design Quality Metrics. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:81-86 [Conf]
  140. Andrew B. Kahng, Stefanus Mantik
    Measurement of Inherent Noise in EDA Tools. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:206-212 [Conf]
  141. Andrew B. Kahng, Igor L. Markov
    Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:208-213 [Conf]
  142. Andrew B. Kahng, Sudhakar Muddu, Niranjan Pol, Devendra Vidhani
    Noise Model for Multiple Segmented Coupled RC Interconnects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:145-150 [Conf]
  143. Andrew B. Kahng, Swamy Muddu, Puneet Sharma
    Impact of Gate-Length Biasing on Threshold-Voltage Selection. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:747-754 [Conf]
  144. Andrew B. Kahng, Gary Smith
    A New Design Cost Model for the 2001 ITRS (invited). [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:190-193 [Conf]
  145. Andrew B. Kahng, Kambiz Samadi, Puneet Sharma
    Study of Floating Fill Impact on Interconnect Capacitance. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:691-696 [Conf]
  146. Andrew B. Kahng, Sherief Reda, Puneet Sharma
    On-Line Adjustable Buffering for Runtime Power Reduction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:550-555 [Conf]
  147. Andrew B. Kahng, Rasit Onur Topaloglu
    A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:467-474 [Conf]
  148. Andrew B. Kahng, Bao Liu
    Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:183-188 [Conf]
  149. Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky
    Engineering a scalable placement heuristic for DNA probe arrays. [Citation Graph (0, 0)][DBLP]
    RECOMB, 2003, pp:148-156 [Conf]
  150. Marcelo O. Johann, Andrew E. Caldwell, Ricardo Augusto da Luz Reis, Andrew B. Kahng
    Admissibility Proofs for the LCS* Algorithm. [Citation Graph (0, 0)][DBLP]
    IBERAMIA-SBIA, 2000, pp:236-244 [Conf]
  151. Kenneth D. Boese, Andrew B. Kahng, Stefanus Mantik
    On the relevance of wire load models. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:91-98 [Conf]
  152. Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang
    Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:71-76 [Conf]
  153. Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu
    Interconnect implications of growth-based structural models for VLSI circuits. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:99-106 [Conf]
  154. Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester
    Investigation of performance metrics for interconnect stack architectures. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:23-29 [Conf]
  155. Andrew B. Kahng, Bao Liu, Xu Xu
    Statistical crosstalk aggressor alignment aware interconnect delay calculation. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:91-97 [Conf]
  156. Andrew B. Kahng, Sherief Reda
    A tale of two nets: studies of wirelength progression in physical design. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:17-24 [Conf]
  157. Andrew B. Kahng, Dirk Stroobandt
    Wiring layer assignments with consistent stage delays. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:115-122 [Conf]
  158. Andrew B. Kahng, Rasit Onur Topaloglu
    Generation of design guarantees for interconnect matching. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:29-34 [Conf]
  159. Andrew B. Kahng, Xu Xu
    Accurate pseudo-constructive wirelength and congestion estimation. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:61-68 [Conf]
  160. Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky
    Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:580-0 [Conf]
  161. Puneet Gupta, Andrew B. Kahng
    Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:431-436 [Conf]
  162. Puneet Gupta, Andrew B. Kahng
    Efficient Design and Analysis of Robust Power Distribution Meshes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:337-342 [Conf]
  163. Andrew B. Kahng
    Mini-Tutorial: IC Layout and Manufacturability: Critical Links and Design Flow Implications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:100-105 [Conf]
  164. Andrew B. Kahng, Sudhakar Muddu
    Improved Effective Capacitance Computations for Use in Logic and Layout Optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:578-583 [Conf]
  165. Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
    Interconnect Optimization Strategies for High-Performance VLSI Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:464-469 [Conf]
  166. Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky
    New and Exact Filling Algorithms for Layout Density Control. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:106-110 [Conf]
  167. Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky
    Border Length Minimization in DNA Array Design. [Citation Graph (0, 0)][DBLP]
    WABI, 2002, pp:435-448 [Conf]
  168. Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Alexander Zelikovsky
    The T-join Problem in Sparse Graphs: Applications to Phase Assignment Problem in VLSI Mask Layout. [Citation Graph (0, 0)][DBLP]
    WADS, 1999, pp:25-36 [Conf]
  169. Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky
    Practical Approximation Algorithms for Separable Packing Linear Programs. [Citation Graph (0, 0)][DBLP]
    WADS, 2001, pp:325-337 [Conf]
  170. Y. Uny Cao, Alex S. Fukunaga, Andrew B. Kahng
    Cooperative Mobile Robotics: Antecedents and Directions. [Citation Graph (0, 0)][DBLP]
    Auton. Robots, 1997, v:4, n:1, pp:7-27 [Journal]
  171. Alan Allan, Don Edenfeld, William H. Joyner Jr., Andrew B. Kahng, Mike Rodgers, Yervant Zorian
    2001 Technology Roadmap for Semiconductors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:1, pp:42-53 [Journal]
  172. Don Edenfeld, Andrew B. Kahng, Mike Rodgers, Yervant Zorian
    2003 Technology Roadmap for Semiconductors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:1, pp:47-56 [Journal]
  173. Charles J. Alpert, Andrew B. Kahng, So-Zen Yao
    Spectral Partitioning with Multiple Eigenvectors. [Citation Graph (0, 0)][DBLP]
    Discrete Applied Mathematics, 1999, v:90, n:1-3, pp:3-26 [Journal]
  174. Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar
    DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:3, pp:7-20 [Journal]
  175. William H. Joyner Jr., Andrew B. Kahng
    Guest Editor's Introduction: Roadmaps and Visions for Design and Test. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:6, pp:4-5 [Journal]
  176. Andrew B. Kahng
    Variability. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:3, pp:120- [Journal]
  177. Andrew B. Kahng
    The Road Ahead: The significance of packaging. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:6, pp:104-105 [Journal]
  178. Andrew B. Kahng
    Error Tolerance. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:86-87 [Journal]
  179. Andrew B. Kahng
    Bringing down NRE. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:3, pp:110-111 [Journal]
  180. Andrew B. Kahng
    How much variability can designers tolerate? [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:6, pp:96-97 [Journal]
  181. Andrew B. Kahng, Grant Martin
    DAC Highlights. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:3, pp:197-199 [Journal]
  182. Dwight D. Hill, Andrew B. Kahng
    Guest Editors' Introduction: RTL to GDSII - From Foilware to Standard Practice. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:1, pp:9-12 [Journal]
  183. Inki Hong, Andrew B. Kahng, Byung Ro Moon
    Improved Large-Step Markov Chain Variants for the Symmetric TSP. [Citation Graph (0, 0)][DBLP]
    J. Heuristics, 1997, v:3, n:1, pp:63-81 [Journal]
  184. Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky
    Scalable Heuristics for Design of DNA Probe Arrays. [Citation Graph (0, 0)][DBLP]
    Journal of Computational Biology, 2004, v:11, n:2/3, pp:429-447 [Journal]
  185. Joshua N. Cooper, Robert B. Ellis, Andrew B. Kahng
    Asymmetric Binary Covering Codes. [Citation Graph (0, 0)][DBLP]
    J. Comb. Theory, Ser. A, 2002, v:100, n:2, pp:232-249 [Journal]
  186. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning. [Citation Graph (0, 0)][DBLP]
    ACM Journal of Experimental Algorithms, 2000, v:5, n:, pp:5- [Journal]
  187. Andrew B. Kahng, Gabriel Robins, Elizabeth A. Walkup
    How to test a tree. [Citation Graph (0, 0)][DBLP]
    Networks, 1998, v:32, n:3, pp:189-197 [Journal]
  188. Andrew B. Kahng, Sherief Reda
    Match twice and stitch: a new TSP tour construction heuristic. [Citation Graph (0, 0)][DBLP]
    Oper. Res. Lett., 2004, v:32, n:6, pp:499-509 [Journal]
  189. Andrew B. Kahng, Gabriel Robins
    Optimal algorithms for extracting spatial regularity in images. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition Letters, 1991, v:12, n:12, pp:757-764 [Journal]
  190. Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng
    Multilevel circuit partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:8, pp:655-667 [Journal]
  191. Charles J. Alpert, Andrew B. Kahng
    Multiway partitioning via geometric embeddings, orderings, and dynamic programming. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1342-1358 [Journal]
  192. Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
    Minimum buffered routing with bounded capacitive load for slew rate and reliability control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:241-253 [Journal]
  193. Christoph Albrecht, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
    On the skew-bounded minimum-buffer routing tree problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:937-945 [Journal]
  194. Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Hypergraph partitioning with fixed vertices [VLSI CAD]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:267-272 [Journal]
  195. Charles J. Alpert, Tony F. Chan, Andrew B. Kahng, Igor L. Markov, Pep Mulet
    Faster minimization of linear wirelength for global placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:1, pp:3-13 [Journal]
  196. Charles J. Alpert, T. C. Hu, Dennis J.-H. Huang, Andrew B. Kahng, David Karger
    Prim-Dijkstra tradeoffs for improved performance-driven routing tree design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:7, pp:890-896 [Journal]
  197. Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins
    Near-optimal critical sink routing tree constructions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1417-1436 [Journal]
  198. Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Huijuan Wang, Alexander Zelikovsky
    Optimal phase conflict removal for layout of dark field alternatingphase shifting masks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:175-187 [Journal]
  199. Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong
    Effective iterative techniques for fingerprinting design IP. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:208-215 [Journal]
  200. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Optimal partitioners and end-case placers for standard-cell layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1304-1313 [Journal]
  201. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Hierarchical whitespace allocation in top-down placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1550-1556 [Journal]
  202. Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky
    On wirelength estimations for row-based placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1265-1278 [Journal]
  203. Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao
    The Y architecture for on-chip interconnect: analysis and methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:588-599 [Journal]
  204. Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky
    Area fill synthesis for uniform layout density. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1132-1147 [Journal]
  205. Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng
    Compressible area fill synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1169-1187 [Journal]
  206. Jason Cong, Andrew B. Kahng, Kwok-Shing Leung
    Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:1, pp:24-39 [Journal]
  207. Jason Cong, Andrew B. Kahng, Gabriel Robins
    Matching-based methods for high-performance clock routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1157-1169 [Journal]
  208. Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, Chak-Kuen Wong
    Provably good performance-driven global routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:739-752 [Journal]
  209. Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky
    Provably good global buffering by generalized multiterminalmulticommodity flow approximation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:263-274 [Journal]
  210. Lars W. Hagen, Andrew B. Kahng, Fadi J. Kurdahi, Champaka Ramachandran
    On the intrinsic Rent parameter and spectra-based partitioning methodologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:27-37 [Journal]
  211. Lars W. Hagen, Andrew B. Kahng
    Combining problem reduction and adaptive multistart: a new technique for superior iterative partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:709-717 [Journal]
  212. Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma
    Layout-aware scan chain synthesis for improved path delay fault coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1104-1114 [Journal]
  213. Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester
    Gate-length biasing for runtime-leakage control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1475-1485 [Journal]
  214. Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng
    On implementation choices for iterative improvement partitioning algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1199-1205 [Journal]
  215. Lars W. Hagen, Andrew B. Kahng
    New spectral methods for ratio cut partitioning and clustering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1074-1085 [Journal]
  216. Andrew B. Kahng, Bao Liu, Ion I. Mandoiu
    Nontree routing for reliability and yield improvement [IC layout]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:148-156 [Journal]
  217. Andrew B. Kahng, John Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe
    Constraint-based watermarking techniques for design IP protection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1236-1252 [Journal]
  218. Andrew B. Kahng, Sudhakar Muddu
    An analytical delay model for RLC interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:12, pp:1507-1514 [Journal]
  219. Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky
    Computer-Aided Optimization of DNA Array Design and Manufacturing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:2, pp:305-320 [Journal]
  220. Andrew B. Kahng, Stefanus Mantik, Dirk Stroobandt
    Toward accurate models of achievable routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:648-659 [Journal]
  221. Andrew B. Kahng, Sherief Reda
    New and improved BIST diagnosis methods from combinatorial Group testing theory. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:533-543 [Journal]
  222. Andrew B. Kahng, Sherief Reda
    Wirelength minimization for min-cut placements via placement feedback. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1301-1312 [Journal]
  223. Andrew B. Kahng, Gabriel Robins
    A new class of iterative Steiner tree heuristics with good performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:893-902 [Journal]
  224. Andrew B. Kahng, Gabriel Robins
    On the performance bounds for a class of rectilinear Steiner tree heuristics in arbitrary dimension. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1462-1465 [Journal]
  225. Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky
    Filling algorithms and analyses for layout density control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:445-462 [Journal]
  226. Andrew B. Kahng, Majid Sarrafzadeh
    Guest Editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:1, pp:1-2 [Journal]
  227. Andrew B. Kahng, Chung-Wen Albert Tsao
    Planar-DME: a single-layer zero-skew clock tree router. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:8-19 [Journal]
  228. Andrew B. Kahng, Qinke Wang
    Implementation and extensibility of an analytic placer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:5, pp:734-747 [Journal]
  229. Andrew B. Kahng, Xu Xu
    Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:464-471 [Journal]
  230. Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng
    A Fast Hierarchical Quadratic Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:4, pp:678-691 [Journal]
  231. Puneet Gupta, Andrew B. Kahng, Stefanus Mantik
    Routing-aware scan chain ordering. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:546-560 [Journal]
  232. Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao
    Bounded-skew clock and Steiner routing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:3, pp:341-388 [Journal]
  233. Andrew B. Kahng, Sudhakar Muddu
    Analysis of RC interconnections under ramp input. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:2, pp:168-192 [Journal]
  234. Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester
    Line-End Shortening is Not Always a Failure. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:270-271 [Conf]
  235. Andrew B. Kahng
    Design challenges at 65nm and beyond. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1466-1467 [Conf]
  236. Charles Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky
    Bright-Field AAPSM Conflict Detection and Correction [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  237. Andrew B. Kahng, Bao Liu, Qinke Wang
    Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:904-912 [Journal]
  238. Charles J. Alpert, Andrew B. Kahng
    A general framework for vertex orderings with applications to circuit clustering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:240-246 [Journal]
  239. Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt
    Toward better wireload models in the presence of obstacles. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:177-189 [Journal]
  240. Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester
    Improved a priori interconnect predictions and technology extrapolation in the GTX system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:3-14 [Journal]

  241. Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography. [Citation Graph (, )][DBLP]


  242. A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. [Citation Graph (, )][DBLP]


  243. Investigation of diffusion rounding for post-lithography analysis. [Citation Graph (, )][DBLP]


  244. Interconnect modeling for improved system-level design optimization. [Citation Graph (, )][DBLP]


  245. Bounded-lifetime integrated circuits. [Citation Graph (, )][DBLP]


  246. DFM in practice: hit or hype? [Citation Graph (, )][DBLP]


  247. Dose map and placement co-optimization for timing yield enhancement and leakage power reduction. [Citation Graph (, )][DBLP]


  248. Recovery-driven design: a power minimization methodology for error-tolerant processor modules. [Citation Graph (, )][DBLP]


  249. Trace-driven optimization of networks-on-chip configurations. [Citation Graph (, )][DBLP]


  250. Eyecharts: constructive benchmarking of gate sizing heuristics. [Citation Graph (, )][DBLP]


  251. ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. [Citation Graph (, )][DBLP]


  252. Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures. [Citation Graph (, )][DBLP]


  253. On implementation choices for iterative improvement partitioning algorithms. [Citation Graph (, )][DBLP]


  254. Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay. [Citation Graph (, )][DBLP]


  255. Optimal equivalent circuits for interconnect delay calculations using moments. [Citation Graph (, )][DBLP]


  256. Exploiting STI stress for performance. [Citation Graph (, )][DBLP]


  257. Layout decomposition for double patterning lithography. [Citation Graph (, )][DBLP]


  258. Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography. [Citation Graph (, )][DBLP]


  259. Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction. [Citation Graph (, )][DBLP]


  260. Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. [Citation Graph (, )][DBLP]


  261. Detailed placement for leakage reduction using systematic through-pitch variation. [Citation Graph (, )][DBLP]


  262. How to get real mad. [Citation Graph (, )][DBLP]


  263. Quantified Impacts of Guardband Reduction on Design Process Outcomes. [Citation Graph (, )][DBLP]


  264. Revisiting the linear programming framework for leakage power vs. performance optimization. [Citation Graph (, )][DBLP]


  265. Toward effective utilization of timing exceptions in design optimization. [Citation Graph (, )][DBLP]


  266. Methodology from chaos in IC implementation. [Citation Graph (, )][DBLP]


  267. Assessing chip-level impact of double patterning lithography. [Citation Graph (, )][DBLP]


  268. Is overlay error more important than interconnect variations in double patterning? [Citation Graph (, )][DBLP]


  269. Multicommodity Flow Algorithms for Buffered Global Routing [Citation Graph (, )][DBLP]


  270. Roundtable: Design and CAD Challenges for Leading-Edge Multimedia Designs. [Citation Graph (, )][DBLP]


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