The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Igor L. Markov: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning. [Citation Graph (0, 0)][DBLP]
    ALENEX, 1999, pp:177-193 [Conf]
  2. DoRon B. Motter, Igor L. Markov
    A Compressed Breadth-First Search for Satisfiability. [Citation Graph (0, 0)][DBLP]
    ALENEX, 2002, pp:29-42 [Conf]
  3. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Improved algorithms for hypergraph bipartitioning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:661-666 [Conf]
  4. Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
    ShatterPB: symmetry-breaking for pseudo-Boolean formulas. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:883-886 [Conf]
  5. Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
    Dynamic symmetry-breaking for improved Boolean optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:445-450 [Conf]
  6. Ross Baldick, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov
    Function Smoothing with Applications to VLSI Layout. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:225-0 [Conf]
  7. Andrew A. Kennings, Igor L. Markov
    Analytical minimization of half-perimeter wirelength. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:179-184 [Conf]
  8. David A. Papa, Igor L. Markov, Philip Chong
    Utility of the OpenAccess database in academic research. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:440-441 [Conf]
  9. Vivek V. Shende, Stephen S. Bullock, Igor L. Markov
    Synthesis of quantum logic circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:272-275 [Conf]
  10. Arathi Ramani, Igor L. Markov
    Automatically Exploiting Symmetries in Constraint Programming. [Citation Graph (0, 0)][DBLP]
    CSCLP, 2004, pp:98-112 [Conf]
  11. Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
    Shatter: efficient symmetry-breaking for boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:836-839 [Conf]
  12. Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
    Solving difficult SAT instances in the presence of symmetry. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:731-736 [Conf]
  13. Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Igor L. Markov, Kenneth Yan
    Quadratic Placement Revisited. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:752-757 [Conf]
  14. Stephen S. Bullock, Igor L. Markov
    An arbitrary twoqubit computation In 23 elementary gates or less. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:324-329 [Conf]
  15. Andrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farinaz Koushanfar, Hua Lu, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester
    GTX: the MARCO GSRC technology extrapolation system. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:693-698 [Conf]
  16. Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov
    Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:349-354 [Conf]
  17. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Can recursive bisection alone produce routable placements? [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:477-482 [Conf]
  18. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Hypergraph Partitioning with Fixed Vertices. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:355-359 [Conf]
  19. Olivier Coudert, Igor L. Markov, Christoph Meinel, Ellen Sentovich
    Web-based frameworks to enable CAD RD (abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:711- [Conf]
  20. Paul T. Darga, Mark H. Liffiton, Karem A. Sakallah, Igor L. Markov
    Exploiting structure in symmetry detection for CNF. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:530-534 [Conf]
  21. Andrew B. Kahng, John Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe
    Watermarking Techniques for Intellectual Property Protection. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:776-781 [Conf]
  22. Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe
    Robust IP Watermarking Methodologies for Physical Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:782-787 [Conf]
  23. Michael D. Moffitt, Aaron N. Ng, Igor L. Markov, Martha E. Pollack
    Constraint-driven floorplan repair. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1103-1108 [Conf]
  24. Yoonna Oh, Maher N. Mneimneh, Zaher S. Andraus, Karem A. Sakallah, Igor L. Markov
    AMUSE: a minimally-unsatisfiable subformula extractor. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:518-523 [Conf]
  25. Andrew B. Kahng, Igor L. Markov, Sherief Reda
    Boosting: Min-Cut Placement with Improved Signal Delay. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1098-1103 [Conf]
  26. Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes
    Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:282-287 [Conf]
  27. Igor L. Markov, Dmitri Maslov
    Uniformly-Switching Logic for Cryptographic Hardware. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:432-433 [Conf]
  28. Arathi Ramani, Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
    Breaking Instance-Independent Symmetries in Exact Graph Coloring. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:324-331 [Conf]
  29. Vivek V. Shende, Igor L. Markov, Stephen S. Bullock
    Smaller Two-Qubit Circuits for Quantum Communication and Computation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:980-987 [Conf]
  30. George F. Viamontes, Igor L. Markov, John P. Hayes
    High-Performance QuIDD-Based Simulation of Quantum Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1354-1355 [Conf]
  31. Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
    FORCE: a fast and easy-to-implement variable-ordering heuristic. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:116-119 [Conf]
  32. Hayward H. Chan, Igor L. Markov
    Practical slicing and non-slicing block-packing without simulated annealing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:282-287 [Conf]
  33. Andrew B. Kahng, Igor L. Markov, Sherief Reda
    On legalization of row-based placements. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:214-219 [Conf]
  34. David A. Papa, Saurabh N. Adya, Igor L. Markov
    Constructive benchmarking for placement. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:113-118 [Conf]
  35. Saurabh N. Adya, S. Chaturvedi, Jarrod A. Roy, David A. Papa, Igor L. Markov
    Unification of partitioning, placement and floorplanning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:550-557 [Conf]
  36. Saurabh N. Adya, Igor L. Markov, Paul Villarrubia
    On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:311-319 [Conf]
  37. Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
    Faster SAT and Smaller BDDs via Common Function Structure. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:443-448 [Conf]
  38. Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
    Generic ILP versus specialized 0-1 ILP: an update. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:450-457 [Conf]
  39. Kai-Hui Chang, Valeria Bertacco, Igor L. Markov
    Simulation-based bug trace minimization with BMC-based refinement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:1045-1051 [Conf]
  40. Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
    Post-placement rewiring and rebuffering by exhaustive search for functional symmetries. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:56-63 [Conf]
  41. Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes
    Reversible logic circuit synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:353-360 [Conf]
  42. Saurabh N. Adya, Igor L. Markov
    Fixed-outline Floorplanning through Better Local Search. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:328-334 [Conf]
  43. Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
    Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:64-69 [Conf]
  44. Fadi A. Aloul, Karem A. Sakallah, Igor L. Markov
    Efficient Symmetry Breaking for Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    IJCAI, 2003, pp:271-276 [Conf]
  45. Arathi Ramani, Igor L. Markov
    Combining Two Local Search Approaches to Hypergraph Partitioning. [Citation Graph (0, 0)][DBLP]
    IJCAI, 2003, pp:1546-0 [Conf]
  46. Saurabh N. Adya, Igor L. Markov
    Consistent placement of macro-blocks using floorplanning and standard-cell placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:12-17 [Conf]
  47. Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden
    Benchmarking for large-scale placement and beyond. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:95-103 [Conf]
  48. Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, Kenneth Yan
    Faster minimization of linear wirelength for global placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:4-11 [Conf]
  49. Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Partitioning with terminals: a "new" problem and new benchmarks. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:151-157 [Conf]
  50. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Optimal partitioners and end-case placers for standard-cell layout. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:90-96 [Conf]
  51. Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky
    On wirelength estimations for row-based placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:4-11 [Conf]
  52. Hayward H. Chan, Saurabh N. Adya, Igor L. Markov
    Are floorplan representations important in digital design? [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:129-136 [Conf]
  53. Andrew B. Kahng, Stefanus Mantik, Igor L. Markov
    Min-max placement for large-scale timing optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:143-148 [Conf]
  54. Jarrod A. Roy, James F. Lu, Igor L. Markov
    Seeing the forest and the trees: Steiner wirelength optimization in placemen. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:78-85 [Conf]
  55. Jarrod A. Roy, David A. Papa, Saurabh N. Adya, Hayward H. Chan, Aaron N. Ng, James F. Lu, Igor L. Markov
    Capo: robust and scalable open-source min-cut floorplacer. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:224-226 [Conf]
  56. Jarrod A. Roy, David A. Papa, Aaron N. Ng, Igor L. Markov
    Satisfying whitespace requirements in top-down placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:206-208 [Conf]
  57. Aaron N. Ng, Igor L. Markov, Rajat Aggarwal, Venky Ramachandran
    Solving hard instances of floorplacement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:170-177 [Conf]
  58. Zhong Xiu, David A. Papa, Philip Chong, Christoph Albrecht, Andreas Kuehlmann, Rob A. Rutenbar, Igor L. Markov
    Early research experience with OpenAccess gear: an open source development environment for physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:94-100 [Conf]
  59. Aaron N. Ng, Igor L. Markov
    Toward Quality EDA Tools and Tool Flows Through High-Performance Computing. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:22-27 [Conf]
  60. Andrew B. Kahng, Igor L. Markov
    Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:208-213 [Conf]
  61. Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco
    InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:487-494 [Conf]
  62. Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
    Efficient Gate and Input Ordering for Circuit-to-BDD Conversion. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:137-142 [Conf]
  63. DoRon B. Motter, Igor L. Markov
    Overcoming Resolution-Based Lower Bounds for SAT Solvers. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:373-378 [Conf]
  64. Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes
    Reversible Logic Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:125-130 [Conf]
  65. Ketan N. Patel, Igor L. Markov
    Error-correction and crosstalk avoidance in DSM busses. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:9-14 [Conf]
  66. Ketan N. Patel, John P. Hayes, Igor L. Markov
    Fault Testing for Reversible Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:410-416 [Conf]
  67. DoRon B. Motter, Jarrod A. Roy, Igor L. Markov
    Resolution cannot polynomially simulate compressed-BFS. [Citation Graph (0, 0)][DBLP]
    Ann. Math. Artif. Intell., 2005, v:44, n:1-2, pp:121-156 [Journal]
  68. Krysta Marie Svore, Alfred V. Aho, Andrew W. Cross, Isaac L. Chuang, Igor L. Markov
    A Layered Software Architecture for Quantum Computing Design Tools. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2006, v:39, n:1, pp:74-83 [Journal]
  69. Andrew E. Caldwell, Igor L. Markov
    Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:3, pp:72-81 [Journal]
  70. Saurabh N. Adya, Igor L. Markov, Paul G. Villarrubia
    On whitespace and stability in physical synthesis. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:4, pp:340-362 [Journal]
  71. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning. [Citation Graph (0, 0)][DBLP]
    ACM Journal of Experimental Algorithms, 2000, v:5, n:, pp:5- [Journal]
  72. Aditya K. Prasad, Vivek V. Shende, Igor L. Markov, John P. Hayes, Ketan N. Patel
    Data structures and algorithms for simplifying reversible circuits. [Citation Graph (0, 0)][DBLP]
    JETC, 2006, v:2, n:4, pp:277-293 [Journal]
  73. Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
    MINCE: A Static Global Variable-Ordering Heuristic for SAT Search and BDD Manipulation. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2004, v:10, n:12, pp:1562-1596 [Journal]
  74. Fadi A. Aloul, Karem A. Sakallah, Igor L. Markov
    Efficient Symmetry Breaking for Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:5, pp:549-558 [Journal]
  75. Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
    Solving difficult instances of Boolean satisfiability in the presence of symmetry. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1117-1137 [Journal]
  76. Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden
    Benchmarking for large-scale placement and beyond. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:472-487 [Journal]
  77. Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Hypergraph partitioning with fixed vertices [VLSI CAD]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:267-272 [Journal]
  78. Charles J. Alpert, Tony F. Chan, Andrew B. Kahng, Igor L. Markov, Pep Mulet
    Faster minimization of linear wirelength for global placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:1, pp:3-13 [Journal]
  79. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Optimal partitioners and end-case placers for standard-cell layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1304-1313 [Journal]
  80. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Hierarchical whitespace allocation in top-down placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1550-1556 [Journal]
  81. Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky
    On wirelength estimations for row-based placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1265-1278 [Journal]
  82. Andrew B. Kahng, John Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe
    Constraint-based watermarking techniques for design IP protection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1236-1252 [Journal]
  83. Ketan N. Patel, John P. Hayes, Igor L. Markov
    Fault testing for reversible circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1220-1230 [Journal]
  84. Jarrod A. Roy, Saurabh N. Adya, David A. Papa, Igor L. Markov
    Min-cut floorplacement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1313-1326 [Journal]
  85. Vivek V. Shende, Stephen S. Bullock, Igor L. Markov
    Synthesis of quantum-logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1000-1010 [Journal]
  86. Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes
    Synthesis of reversible logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:710-722 [Journal]
  87. Saurabh N. Adya, Igor L. Markov
    Combinatorial techniques for mixed-size placement. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:58-90 [Journal]
  88. Ketan N. Patel, Igor L. Markov
    Error-correction and crosstalk avoidance in DSM busses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1076-1080 [Journal]
  89. Ramashis Das, Igor L. Markov, John P. Hayes
    On-Chip Test Generation Using Linear Subspaces. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:111-116 [Conf]
  90. Igor L. Markov, Yaoyun Shi
    Constant-degree graph expansions that preserve the treewidth [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  91. Igor L. Markov, Louis Scheffer, Dirk Stroobandt
    Special issue on System-Level Interconnect Prediction. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:381- [Journal]
  92. Arathi Ramani, Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul
    Breaking Instance-Independent Symmetries In Exact Graph Coloring. [Citation Graph (0, 0)][DBLP]
    J. Artif. Intell. Res. (JAIR), 2006, v:26, n:, pp:289-322 [Journal]
  93. Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
    Symmetry breaking for pseudo-Boolean formulas. [Citation Graph (0, 0)][DBLP]
    ACM Journal of Experimental Algorithms, 2007, v:12, n:, pp:- [Journal]
  94. Fadi A. Aloul, Arathi Ramani, Karem A. Sakallah, Igor L. Markov
    Solution and Optimization of Systems of Pseudo-Boolean Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:10, pp:1415-1424 [Journal]
  95. Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
    Postplacement rewiring by exhaustive search for functional symmetries. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]
  96. Saurabh N. Adya, Igor L. Markov
    Fixed-outline floorplanning: enabling hierarchical design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1120-1135 [Journal]
  97. Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester
    Improved a priori interconnect predictions and technology extrapolation in the GTX system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:3-14 [Journal]

  98. ECO-system: Embracing the Change in Placement. [Citation Graph (, )][DBLP]


  99. Node Mergers in the Presence of Don't Cares. [Citation Graph (, )][DBLP]


  100. Safe Delay Optimization for Physical Synthesis. [Citation Graph (, )][DBLP]


  101. Fixing Design Errors with Counterexamples and Resynthesis. [Citation Graph (, )][DBLP]


  102. Protecting bus-based hardware IP by secret sharing. [Citation Graph (, )][DBLP]


  103. On the role of timing masking in reliable logic circuit design. [Citation Graph (, )][DBLP]


  104. Faster symmetry discovery using sparsity of symmetries. [Citation Graph (, )][DBLP]


  105. Improving testability and soft-error resilience through retiming. [Citation Graph (, )][DBLP]


  106. On the costs and benefits of stochasticity in stream processing. [Citation Graph (, )][DBLP]


  107. EPIC: Ending Piracy of Integrated Circuits. [Citation Graph (, )][DBLP]


  108. Random Stimulus Generation using Entropy and XOR Constraints. [Citation Graph (, )][DBLP]


  109. Customizing IP cores for system-on-chip designs using extensive external don't-cares. [Citation Graph (, )][DBLP]


  110. Spinto: High-performance energy minimization in spin glasses. [Citation Graph (, )][DBLP]


  111. Contango: Integrated optimization of SoC clock networks. [Citation Graph (, )][DBLP]


  112. Large-scale Boolean matching. [Citation Graph (, )][DBLP]


  113. Automating post-silicon debugging and repair. [Citation Graph (, )][DBLP]


  114. Checking equivalence of quantum circuits and states. [Citation Graph (, )][DBLP]


  115. High-performance routing at the nanometer scale. [Citation Graph (, )][DBLP]


  116. On the decreasing significance of large standard cells in technology mapping. [Citation Graph (, )][DBLP]


  117. Enhancing design robustness with reliability-aware resynthesis and logic simulation. [Citation Graph (, )][DBLP]


  118. CRISP: Congestion reduction by iterated spreading during placement. [Citation Graph (, )][DBLP]


  119. Reap what you sow: spare cells for post-silicon metal fix. [Citation Graph (, )][DBLP]


  120. RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. [Citation Graph (, )][DBLP]


  121. The coming of age of (academic) global routing. [Citation Graph (, )][DBLP]


  122. Optimizing non-monotonic interconnect using functional simulation and logic restructuring. [Citation Graph (, )][DBLP]


  123. Completing high-quality global routes. [Citation Graph (, )][DBLP]


  124. Symmetry and Satisfiability: An Update. [Citation Graph (, )][DBLP]


  125. Sidewinder: a scalable ILP-based router. [Citation Graph (, )][DBLP]


  126. Circuit CAD Tools as a Security Threat. [Citation Graph (, )][DBLP]


  127. Dynamic symmetry-breaking for Boolean satisfiability. [Citation Graph (, )][DBLP]


  128. Automating Postsilicon Debugging and Repair. [Citation Graph (, )][DBLP]


  129. Tracking Uncertainty with Probabilistic Logic Circuit Testing. [Citation Graph (, )][DBLP]


  130. Incremental Verification with Error Detection, Diagnosis, and Visualization. [Citation Graph (, )][DBLP]


  131. Book Review: A physical-design picture book. [Citation Graph (, )][DBLP]


  132. Master numerical tasks with ease. [Citation Graph (, )][DBLP]


Search in 0.009secs, Finished in 0.017secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002