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## Search the dblp DataBase
Zurab Khasidashvili:
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## Publications of Author- Zurab Khasidashvili, John R. W. Glauert
**Discrete Normalization and Standardization in Deterministic Residual Structures.**[Citation Graph (0, 0)][DBLP] ALP, 1996, pp:135-149 [Conf] - Zurab Khasidashvili, Mizuhito Ogawa
**Perpetuality and Uniform Normalization.**[Citation Graph (0, 0)][DBLP] ALP/HOA, 1997, pp:240-255 [Conf] - John J. Glauert, Delia Kesner, Zurab Khasidashvili
**Expression Reduction Systems and Extensions: An Overview.**[Citation Graph (0, 0)][DBLP] Processes, Terms and Cycles, 2005, pp:496-553 [Conf] - John R. W. Glauert, Zurab Khasidashvili
**Relative Normalization in Deterministic Residual Structures.**[Citation Graph (0, 0)][DBLP] CAAP, 1996, pp:180-195 [Conf] - Zurab Khasidashvili
**On Higher Order Recursive Program Schemes.**[Citation Graph (0, 0)][DBLP] CAAP, 1994, pp:172-186 [Conf] - Zurab Khasidashvili
**beta-reductions and beta developments of lambda terms with the least number of steps.**[Citation Graph (0, 0)][DBLP] Conference on Computer Logic, 1988, pp:105-111 [Conf] - Zurab Khasidashvili, Adolfo Piperno
**Normalization of Typable Terms by Superdevelopments.**[Citation Graph (0, 0)][DBLP] CSL, 1998, pp:260-282 [Conf] - John R. W. Glauert, Zurab Khasidashvili
**Relative Normalization in Orthogonal Expression Reduction Systems.**[Citation Graph (0, 0)][DBLP] CTRS, 1994, pp:144-165 [Conf] - Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna
**Post-reboot Equivalence and Compositional Verification of Hardware.**[Citation Graph (0, 0)][DBLP] FMCAD, 2006, pp:11-18 [Conf] - John R. W. Glauert, Zurab Khasidashvili
**Minimal Relative Normalization in Orthogonal Expression Reduction Systems.**[Citation Graph (0, 0)][DBLP] FSTTCS, 1996, pp:238-249 [Conf] - Zurab Khasidashvili, Alexander Nadel, Amit Palti, Ziyad Hanna
**Simultaneous SAT-Based Model Checking of Safety Properties.**[Citation Graph (0, 0)][DBLP] Haifa Verification Conference, 2005, pp:56-75 [Conf] - Zurab Khasidashvili, John R. W. Glauert
**The Geometry of Orthogonal Reduction Spaces.**[Citation Graph (0, 0)][DBLP] ICALP, 1997, pp:649-659 [Conf] - Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna
**Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:58-65 [Conf] - Zurab Khasidashvili
**On the Equivalence of Persistent Term Rewriting Systems and Recursive Program Schemes.**[Citation Graph (0, 0)][DBLP] ISTCS, 1993, pp:240-249 [Conf] - Zurab Khasidashvili
**The Longest Perpetual Reductions in Orthogonal Expression Reduction Systems.**[Citation Graph (0, 0)][DBLP] LFCS, 1994, pp:191-203 [Conf] - Zurab Khasidashvili, John R. W. Glauert
**Relating Conflict-Free Stable Transition and Event Models (Extended Abstract).**[Citation Graph (0, 0)][DBLP] MFCS, 1997, pp:269-278 [Conf] - Richard Kennaway, Zurab Khasidashvili, Adolfo Piperno
**Static Analysis of Modularity of beta-Reduction in the Hyperbalanced lambda-Calculus.**[Citation Graph (0, 0)][DBLP] RTA, 2002, pp:51-65 [Conf] - Zurab Khasidashvili
**Optimal Normalization in Orthogonal Term Rewriting Systems.**[Citation Graph (0, 0)][DBLP] RTA, 1993, pp:243-258 [Conf] - Zurab Khasidashvili, John J. Glauert
**Stable Computational Semantics of Conflict-Free Rewrite Systems (Partial Orders with Duplication).**[Citation Graph (0, 0)][DBLP] RTA, 2003, pp:467-482 [Conf] - Zurab Khasidashvili, Mizuhito Ogawa, Vincent van Oostrom
**Uniform Normalisation beyond Orthogonality.**[Citation Graph (0, 0)][DBLP] RTA, 2001, pp:122-136 [Conf] - Zurab Khasidashvili
**Perpetuality and Strong Normalization in Orthogonal Term Rewriting Systems.**[Citation Graph (0, 0)][DBLP] STACS, 1994, pp:163-174 [Conf] - Marco Bozzano, Roberto Bruttomesso, Alessandro Cimatti, Anders Franzén, Ziyad Hanna, Zurab Khasidashvili, Amit Palti, Roberto Sebastiani
**Encoding RTL Constructs for MathSAT: a Preliminary Report.**[Citation Graph (0, 0)][DBLP] Electr. Notes Theor. Comput. Sci., 2006, v:144, n:2, pp:3-14 [Journal] - John R. W. Glauert, Zurab Khasidashvili
**An Abstract Böhm-normalization.**[Citation Graph (0, 0)][DBLP] Electr. Notes Theor. Comput. Sci., 2002, v:70, n:6, pp:- [Journal] - Zurab Khasidashvili, Ziyad Hanna
**SAT-based methods for sequential hardware equivalence verification without synchronization.**[Citation Graph (0, 0)][DBLP] Electr. Notes Theor. Comput. Sci., 2003, v:89, n:4, pp:- [Journal] - Zurab Khasidashvili, Vincent van Oostrom
**Context-sensitive conditional expression reduction systems.**[Citation Graph (0, 0)][DBLP] Electr. Notes Theor. Comput. Sci., 1995, v:2, n:, pp:- [Journal] - Zurab Khasidashvili, Mizuhito Ogawa, Vincent van Oostrom
**Perpetuality and Uniform Normalization in Orthogonal Rewrite Systems.**[Citation Graph (0, 0)][DBLP] Inf. Comput., 2001, v:164, n:1, pp:118-151 [Journal] - John R. W. Glauert, Richard Kennaway, Zurab Khasidashvili
**Stable results and relative normalization.**[Citation Graph (0, 0)][DBLP] J. Log. Comput., 2000, v:10, n:3, pp:323-348 [Journal] - Zurab Khasidashvili, Adolfo Piperno
**A syntactical analysis of normalization.**[Citation Graph (0, 0)][DBLP] J. Log. Comput., 2000, v:10, n:3, pp:381-410 [Journal] - Zurab Khasidashvili
**On the longest perpetual reductions in orthogonal expression reduction systems.**[Citation Graph (0, 0)][DBLP] Theor. Comput. Sci., 2001, v:266, n:1-2, pp:737-772 [Journal] - Zurab Khasidashvili, John R. W. Glauert
**Relating conflict-free stable transition and event models via redex families.**[Citation Graph (0, 0)][DBLP] Theor. Comput. Sci., 2002, v:286, n:1, pp:65-95 [Journal] - Zurab Khasidashvili, John J. Glauert
**The conflict-free Reduction Geometry.**[Citation Graph (0, 0)][DBLP] Theor. Comput. Sci., 2005, v:347, n:3, pp:465-497 [Journal] **On Formal Equivalence Verification of Hardware.**[Citation Graph (, )][DBLP]**Verifying equivalence of memories using a first order logic theorem prover.**[Citation Graph (, )][DBLP]**A compositional theory for post-reboot observational equivalence checking of hardware.**[Citation Graph (, )][DBLP]**Assume-guarantee validation for STE properties within an SVA environment.**[Citation Graph (, )][DBLP]**Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification.**[Citation Graph (, )][DBLP]**Seqver : A Sequential Equivalence Verifier for Hardware Designs .**[Citation Graph (, )][DBLP]
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