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Chak-Kuen Wong: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Andreas Alexander Albrecht, Chak-Kuen Wong
    Inhomogeneous Markov Chains Applied to Pattern Classification. [Citation Graph (0, 0)][DBLP]
    AMAI, 2000, pp:- [Conf]
  2. Andreas Alexander Albrecht, Eike Hein, Daniela Melzer, Kathleen Steinhöfel, Matthias Taupitz, Chak-Kuen Wong
    Liver tissue classification by bounded-depth threshold circuits. [Citation Graph (0, 0)][DBLP]
    CARS, 2001, pp:1156-1157 [Conf]
  3. Kathleen Steinhöfel, Andreas Alexander Albrecht, Chak-Kuen Wong
    Convergence Analysis of Simulated Annealing-Based Algorithms Solving Flow Shop Scheduling Problems. [Citation Graph (0, 0)][DBLP]
    CIAC, 2000, pp:277-290 [Conf]
  4. Andreas Alexander Albrecht, Martin J. Loomes, Kathleen Steinhöfel, Matthias Taupitz, Chak-Kuen Wong
    A local search method for pattern classification. [Citation Graph (0, 0)][DBLP]
    ESANN, 2001, pp:1-6 [Conf]
  5. Wei-Liang Lin, Majid Sarrafzadeh, Chak-Kuen Wong
    The reproducing placement problem with applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:686-689 [Conf]
  6. Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu
    Routing for symmetric FPGAs and FPICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:486-490 [Conf]
  7. Andreas Alexander Albrecht, Chak-Kuen Wong
    On Logarithmic Simulated Annealing. [Citation Graph (0, 0)][DBLP]
    IFIP TCS, 2000, pp:301-314 [Conf]
  8. Andreas Alexander Albrecht, Uwe Der, Kathleen Steinhöfel, Chak-Kuen Wong
    Distributed Simulated Annealing for Job Shop Scheduling. [Citation Graph (0, 0)][DBLP]
    PPSN, 2000, pp:243-252 [Conf]
  9. Tina M. Nicholl, D. T. Lee, Yuh-Zen Liao, Chak-Kuen Wong
    On the X-Y Convex Hull of a Set of X-Y Polygons. [Citation Graph (0, 0)][DBLP]
    BIT, 1983, v:23, n:4, pp:456-471 [Journal]
  10. Kathleen Steinhöfel, Andreas Alexander Albrecht, Chak-Kuen Wong
    Fast parallel heuristics for the job shop scheduling problem. [Citation Graph (0, 0)][DBLP]
    Computers & OR, 2002, v:29, n:2, pp:151-169 [Journal]
  11. Gian Carlo Bongiovanni, Chak-Kuen Wong
    Communication: A Number Representation Convertor for Magnetic Bubble String Comparators. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 1981, v:25, n:1, pp:- [Journal]
  12. Kin-Man Chung, Fabrizio Luccio, Chak-Kuen Wong
    On the Complexity of Permuting Records in Magnetic Bubble Memory Systems. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 1980, v:24, n:1, pp:75-84 [Journal]
  13. Glen S. Miranker, Luong Tang, Chak-Kuen Wong
    A ``Zero-Time'' VLSI Sorter. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 1983, v:27, n:2, pp:140-148 [Journal]
  14. Chak-Kuen Wong, Donald T. Tang
    Dynamic Memories with Faster Random and Sequential Access. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 1977, v:21, n:3, pp:281-287 [Journal]
  15. Chak-Kuen Wong, Po Cheung Yue
    Data Organization in Magnetic Bubble Lattice Files. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 1976, v:20, n:6, pp:576-581 [Journal]
  16. Zong-Ben Xu, Huidong Jin, Kwong-Sak Leung, Yee Leung, Chak-Kuen Wong
    An automata network for performing combinatorial optimization. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 2002, v:47, n:1-4, pp:59-83 [Journal]
  17. G. Y. Yan, Andreas Alexander Albrecht, G. H. F. Young, Chak-Kuen Wong
    The Steiner Tree Problem in Orientation Metrics. [Citation Graph (0, 0)][DBLP]
    J. Comput. Syst. Sci., 1997, v:55, n:3, pp:529-546 [Journal]
  18. Charles Chiang, Majid Sarrafzadeh, Chak-Kuen Wong
    Global routing based on Steiner min-max trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1318-1325 [Journal]
  19. Charles Chiang, Chak-Kuen Wong, Majid Sarrafzadeh
    A weighted Steiner tree-based global router with simultaneous length and density minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1461-1469 [Journal]
  20. Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, Chak-Kuen Wong
    Provably good performance-driven global routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:739-752 [Journal]
  21. Jan-Ming Ho, Majid Sarrafzadeh, Gopalakrishnan Vijayan, Chak-Kuen Wong
    Pad minimization for planar routing of multiple power nets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:419-426 [Journal]
  22. Jan-Ming Ho, Majid Sarrafzadeh, Gopalakrishnan Vijayan, Chak-Kuen Wong
    Layer assignment for multichip modules. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1272-1277 [Journal]
  23. Jan-Ming Ho, Gopalakrishnan Vijayan, Chak-Kuen Wong
    New algorithms for the rectilinear Steiner tree problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:185-193 [Journal]
  24. Jin-fuw Lee, Donald T. Tang, Chak-Kuen Wong
    A timing analysis algorithm for circuits with level-sensitive latches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:535-543 [Journal]
  25. Jin-fuw Lee, Chak-Kuen Wong
    A performance-aimed cell compactor with automatic jogs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:12, pp:1495-1507 [Journal]
  26. Yuh-Zen Liao, Chak-Kuen Wong
    An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:62-69 [Journal]
  27. W. K. Luk, Paolo Sipala, Markku Tamminen, Donald T. Tang, Lin S. Woo, Chak-Kuen Wong
    A Hierarchical Global Wiring Algorithm for Custom Chip Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:518-533 [Journal]
  28. Majid Sarrafzadeh, Kuo-Feng Liao, Chak-Kuen Wong
    Single-layer global routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:38-47 [Journal]
  29. Majid Sarrafzadeh, Chak-Kuen Wong
    Hierarchical Steiner tree construction in uniform orientations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1095-1103 [Journal]
  30. Martine D. F. Schlag, Ellen J. Yoffa, Peter S. Hauge, Chak-Kuen Wong
    A Method for Improving Cascode-Switch Macro Wirability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:2, pp:150-155 [Journal]
  31. Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu
    Routing for symmetric FPGAs and FPICs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:20-31 [Journal]
  32. Gopalakrishnan Vijayan, H. H. Chen, Chak-Kuen Wong
    On VHV-routing in channels with irregular boundaries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:146-152 [Journal]
  33. Ting-Chi Wang, Martin D. F. Wong, Yachyang Sun, Chak-Kuen Wong
    Optimal net assignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:265-269 [Journal]

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