The SCEAS System
Navigation Menu

Search the dblp DataBase


Laurence Pierre: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Magali Contensin, Laurence Pierre
    Model-Checking Systems with Unbounded Variables without Abstraction. [Citation Graph (0, 0)][DBLP]
    AMAST, 2004, pp:87-111 [Conf]
  2. Michel Allemand, Felix Nicoli, Laurence Pierre
    Formal Verification of Hardware using LP and Comparison with Nqthm. [Citation Graph (0, 0)][DBLP]
    Applied Informatics, 1994, pp:150-153 [Conf]
  3. Eric Gascard, Laurence Pierre
    Induction-Oriented Formal Verification in Symmetric Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:418-432 [Conf]
  4. Laurence Pierre
    Describing and verifying synchronous circuits with the Boyer-Moore theorem prover. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:35-55 [Conf]
  5. Laurence Pierre
    VHDL Description and Formal Verification of Systolic Multipliers. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:225-242 [Conf]
  6. Eric Gascard, Laurence Pierre
    Mechanical Verification of Hypercube Algorithms. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  7. Magali Contensin, Laurence Pierre
    Combining ACL2 and a v-calculus Model-Checker to Verify System-Level Designs. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2003, pp:75-0 [Conf]
  8. Laurence Pierre
    An Automatic Generalization Method for the Inductive Proof of Replicated and Parallel Architectures. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:72-91 [Conf]
  9. Eric Gascard, Laurence Pierre
    Formal Proof of Applications Distributed in Symmetric Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 2003, v:13, n:1, pp:3-18 [Journal]

  10. Formal semantics for PSL modeling layer and application to the verification of transactional models. [Citation Graph (, )][DBLP]

  11. High-level symbolic simulation for automatic model extraction. [Citation Graph (, )][DBLP]

  12. Complementary Formal Approaches for Dependability Analysis. [Citation Graph (, )][DBLP]

  13. Formal verification of behavioral VHDL specifications: a case study. [Citation Graph (, )][DBLP]

  14. Executable formal specification and validation of NoC communication infrastructures. [Citation Graph (, )][DBLP]

Search in 0.033secs, Finished in 0.034secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002