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Sreeranga P. Rajan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sreeranga P. Rajan, Masahiro Fujita
    ATM Switch Design: Parametric High-Level Modeling and Formal Verification. [Citation Graph (0, 0)][DBLP]
    AMAST, 1997, pp:437-450 [Conf]
  2. Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan
    Functional Verification of System on Chips-Practices, Issues and Challenges. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:11-13 [Conf]
  3. Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama, Masahiro Fujita
    Model Checking Based on Sequential ATPG. [Citation Graph (0, 0)][DBLP]
    CAV, 1999, pp:418-430 [Conf]
  4. Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum
    Program Slicing of Hardware Description Languages. [Citation Graph (0, 0)][DBLP]
    CHARME, 1999, pp:298-312 [Conf]
  5. Sreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad Malik
    Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:2-6 [Conf]
  6. David W. Currie, Alan J. Hu, Sreeranga P. Rajan
    Automatic formal verification of DSP software. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:130-135 [Conf]
  7. Masahiro Fujita, Sreeranga P. Rajan, Alan J. Hu
    Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol. [Citation Graph (0, 0)][DBLP]
    FM-Trends, 1998, pp:281-295 [Conf]
  8. Oksana Tkachuk, Sreeranga P. Rajan
    Application of automated environment generation to commercial software. [Citation Graph (0, 0)][DBLP]
    ISSTA, 2006, pp:203-214 [Conf]
  9. Sreeranga P. Rajan
    Executing HOL Specifications: Towards an Evaluation Semantics for Classical Higher Order Logic. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1992, pp:527-536 [Conf]
  10. Sreeranga P. Rajan, Jeffrey J. Joyce, Carl-Johan H. Seger
    From Abstract Data Types to Shift Registers: A Case Study in Formal Specification and Verification at Differing Levels of Abstraction using Theorem Proving and Symbolic Simulation. [Citation Graph (0, 0)][DBLP]
    HUG, 1993, pp:489-500 [Conf]
  11. Sreeranga P. Rajan, Masahiro Fujita
    Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:552-557 [Conf]
  12. Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan
    Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:11-13 [Conf]
  13. Graham Hughes, Sreeranga P. Rajan, Tom Sidle, Keith Swenson
    Error Detection in Concurrent Java Programs. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:144, n:3, pp:45-58 [Journal]
  14. David W. Currie, Xiushan Feng, Masahiro Fujita, Alan J. Hu, Mark Kwan, Sreeranga P. Rajan
    Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2006, v:34, n:1, pp:61-91 [Journal]
  15. Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum
    Program slicing for VHDL. [Citation Graph (0, 0)][DBLP]
    STTT, 2002, v:4, n:1, pp:125-137 [Journal]
  16. Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama
    A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1319-1328 [Journal]
  17. Peter F. A. Middelhoek, Sreeranga P. Rajan
    From VHDL to efficient and first-time-right designs: a formal approach. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:2, pp:205-250 [Journal]
  18. Sreeranga P. Rajan, Masahiro Fujita, K. Yuan, Mike Tien-Chien Lee
    ATM switch design by high-level modeling, formal verification and high-level synthesi. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:4, pp:554-562 [Journal]
  19. Sreeranga P. Rajan
    Editorial. [Citation Graph (0, 0)][DBLP]
    TOS, 2005, v:1, n:1, pp:1-2 [Journal]

  20. Context-Sensitive Relevancy Analysis for Efficient Symbolic Execution. [Citation Graph (, )][DBLP]


  21. WEAVE: WEb Applications Validation Environment. [Citation Graph (, )][DBLP]


  22. Combining environment generation and slicing for modular software model checking. [Citation Graph (, )][DBLP]


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