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Cosimo Antonio Prete: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Cosimo Antonio Prete
    A process cache memory for tightly coupled multiprocessor systems. [Citation Graph (0, 0)][DBLP]
    ACM Southeast Regional Conference, 1992, pp:131-138 [Conf]
  2. Cosimo Antonio Prete
    Cachesim: A Graphical Software Environment to Support the Teaching of Computer Systems with Cache Memories. [Citation Graph (0, 0)][DBLP]
    CSEE, 1994, pp:317-327 [Conf]
  3. Pierfrancesco Foglia, Daniele Mangano, Cosimo Antonio Prete
    A NUCA Model for Embedded Systems Cache Design. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:41-46 [Conf]
  4. Alessio Bechini, Raffaele Lapadula, Cosimo Antonio Prete
    Dealing with Non-Determinism in Communications within Java Applications. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:2350-0 [Conf]
  5. Roberto Giorgi, Cosimo Antonio Prete, Luigi M. Ricciardi, Gianpaolo Prina
    A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1996, pp:207-214 [Conf]
  6. Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
    Performance Analysis of Electronic Commerce Multiprocessor Server. [Citation Graph (0, 0)][DBLP]
    HICSS, 2000, pp:- [Conf]
  7. Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
    Evaluating Optimizing for Multiprocessors E-Commerce Server Running TPC-W Workload. [Citation Graph (0, 0)][DBLP]
    HICSS, 2001, pp:- [Conf]
  8. Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi
    A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1997, pp:266-275 [Conf]
  9. Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
    Process Migration Effects on Memory Performance of Multiprocessor. [Citation Graph (0, 0)][DBLP]
    HiPC, 1999, pp:133-142 [Conf]
  10. Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
    Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture. [Citation Graph (0, 0)][DBLP]
    NETWORKING Workshops, 2002, pp:134-146 [Conf]
  11. Cosimo Antonio Prete, Luigi M. Ricciardi, Gianpaolo Prina
    Reducing coherence-related overhead in multiprocessor systems. [Citation Graph (0, 0)][DBLP]
    PDP, 1995, pp:444-451 [Conf]
  12. Alessio Bechini, François Bodin, Cosimo Antonio Prete
    Editorial message for the special track on embedded systems: applications, solutions, and techniques. [Citation Graph (0, 0)][DBLP]
    SAC, 2005, pp:836-837 [Conf]
  13. Alessio Bechini, François Bodin, Cosimo Antonio Prete
    Editorial message for the special track on embedded systems: applications, solutions, and techniques. [Citation Graph (0, 0)][DBLP]
    SAC, 2006, pp:889-890 [Conf]
  14. Alessio Bechini, Cosimo Antonio Prete
    Embedded Systems Track Editorial. [Citation Graph (0, 0)][DBLP]
    SAC, 2003, pp:659-660 [Conf]
  15. Alessio Bechini, Cosimo Antonio Prete
    Editorial message for the special track on embedded systems: applications, solutions, and techniques. [Citation Graph (0, 0)][DBLP]
    SAC, 2004, pp:819-820 [Conf]
  16. Sandro Bartolini, Cosimo Antonio Prete
    An Object Level Transformation Technique to Improve the Performance of Embedded Applications. [Citation Graph (0, 0)][DBLP]
    SCAM, 2001, pp:26-34 [Conf]
  17. Cosimo Antonio Prete, Pierfrancesco Foglia, Michele Zanda
    An Innovative Tool to Easily Get Usable Web Sites. [Citation Graph (0, 0)][DBLP]
    WEBIST, 2005, pp:373-376 [Conf]
  18. Alessio Bechini, Pierfrancesco Foglia, Cosimo Antonio Prete
    Use of a CORBA/RMI gateway: characterization of communication overhead. [Citation Graph (0, 0)][DBLP]
    Workshop on Software and Performance, 2002, pp:150-156 [Conf]
  19. Paolo Corsini, Cosimo Antonio Prete, Luca Simoncini
    MuTEAM: An experience in the design of robust multiprocessor systems. [Citation Graph (0, 0)][DBLP]
    Comput. Syst. Sci. Eng., 1985, v:1, n:1, pp:23-35 [Journal]
  20. Alberto Bartoli, Gianluca Dini, M. Luise, G. Pazzaglia, Cosimo Antonio Prete, A. D'Andrea
    Reusing sequential software in a distributed environment. [Citation Graph (0, 0)][DBLP]
    Distributed Systems Engineering, 1995, v:2, n:1, pp:2-13 [Journal]
  21. Alessio Bechini, Cosimo Antonio Prete
    Behavior investigation of concurrent Java programs: an approach based on source-code instrumentation. [Citation Graph (0, 0)][DBLP]
    Future Generation Comp. Syst., 2001, v:18, n:2, pp:307-316 [Journal]
  22. Sandro Bartolini, Cosimo Antonio Prete
    A cache-aware program transformation technique suitable for embedded systems. [Citation Graph (0, 0)][DBLP]
    Information & Software Technology, 2002, v:44, n:13, pp:783-795 [Journal]
  23. Pierfrancesco Foglia, F. Giuntoli, Cosimo Antonio Prete, Michele Zanda
    Assisting e-government users with animated talking faces. [Citation Graph (0, 0)][DBLP]
    Interactions, 2007, v:14, n:1, pp:24-26 [Journal]
  24. Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
    Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2005, v:65, n:3, pp:289-306 [Journal]
  25. Alessio Bechini, Thomas M. Conte, Cosimo Antonio Prete
    Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:4, pp:8-9 [Journal]
  26. Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete
    Guests editor's introduction. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:3, pp:1-2 [Journal]
  27. Sandro Bartolini, Roberto Giorgi, Jelica Protic, Cosimo Antonio Prete, M. Valero
    Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2001, v:29, n:5, pp:9-12 [Journal]
  28. Sandro Bartolini, Cosimo Antonio Prete
    A proposal for input-sensitivity analysis of profile-driven optimizations on embedded applications. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:70-77 [Journal]
  29. Alessio Bechini, Pierfrancesco Foglia, Cosimo Antonio Prete
    Fine-grain design space exploration for a cartographic SoC multiprocessor. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2003, v:31, n:1, pp:85-92 [Journal]
  30. Alessio Bechini, Cosimo Antonio Prete
    Performance-steered design of software architectures for embedded multicore systems. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 2002, v:32, n:12, pp:1155-1173 [Journal]
  31. Paolo Ancilotti, Beatrice Lazzerini, Cosimo Antonio Prete, Maurizio Sacchi
    A Distributed Commit Protocol for a Multicomputer System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:5, pp:718-724 [Journal]
  32. Sandro Bartolini, Cosimo Antonio Prete
    Optimizing instruction cache performance of embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:4, pp:934-965 [Journal]
  33. Roberto Giorgi, Cosimo Antonio Prete
    PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1999, v:10, n:7, pp:742-763 [Journal]
  34. Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi
    A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1995, v:6, n:9, pp:915-929 [Journal]

  35. A power-efficient migration mechanism for D-NUCA caches. [Citation Graph (, )][DBLP]


  36. Leveraging Data Promotion for Low Power D-NUCA Caches. [Citation Graph (, )][DBLP]


  37. An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload. [Citation Graph (, )][DBLP]


  38. Special track on Embedded Systems: Applications, Solutions, and Techniques: editorial message. [Citation Graph (, )][DBLP]


  39. Performance Sensitivity of NUCA Caches to On-Chip Network Parameters. [Citation Graph (, )][DBLP]


  40. Analysis of Performance Dependencies in NUCA-Based CMP Systems. [Citation Graph (, )][DBLP]


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