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Publications of Author

1. Hiroshi Echizen-ya, Kenji Araki, Yoshikazu Miyanaga, Koji Tochinai
   An Improvement in the Selection Process of Machine Translation Using Inductive Learning with Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
   ANLP, 1997, pp:11-12 [Conf]
   
2. Takayuki Sugawara, Yoshikazu Miyanaga, Norinobu Yoshida
   A Design of Analog C-Matrix Circuits used for Signal/Data Processing. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2002, pp:355-359 [Conf]
   
3. Yasuyuki Hatakawa, Shingo Yoshizawa, Yoshikazu Miyanaga
   Robust VLSI architecture for system-on-chip design and its implementation in Viterbi decoder. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2005, pp:25-28 [Conf]
   
4. Rafiqul Islam, Makoto Hiroshige, Yoshikazu Miyanaga, Koji Tochinai
   Phoneme Recognition System Based on a Modified TDNN Using Self-Organizing Clustering Network. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1995, pp:1816-1819 [Conf]
   
5. Honglan Jin, Yoshikazu Miyanaga, Koji Tochinai
   Design of a Compact Cluster Structure by Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1995, pp:1512-1515 [Conf]
   
6. Frederico Buchholz Maciel, Yoshikazu Miyanaga, Koji Tochinai
   A Performance-driven Approach to the High-level Synthesis of DSP Algorithms. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1993, pp:1658-1661 [Conf]
   
7. Yoshikazu Miyanaga, Honglan Jin, Rafiqul Islam, Koji Tochinai
   A Self-Organized Network with a Supervised Training. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1995, pp:482-485 [Conf]
   
8. Yoshikazu Miyanaga, Takeshi Nagae, Tateo Shimozawa, Koji Tochinai
   Neuron architecture based on jamming avoidance response of an electric fish. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1993, pp:2600-2603 [Conf]
   
9. Jun'ya Shimizu, Yoshikazu Miyanaga, Koji Tochinai
   An Estimation of Time-Varying Parameters using Multi-AR Lattice Models in Subbands. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1994, pp:245-248 [Conf]
   
10. Shingo Yoshizawa, Naoya Wada, Noboru Hayasaka, Yoshikazu Miyanaga
    Scalable architecture for word HMM-based speech recognition. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:417-420 [Conf]
    
11. H. Ryu, Y. Miyanaga, K. Tochinai
    An image compression using self-organization with genetic algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 1999, pp:5-8 [Conf]
    
12. Takayuki Sugawara, Yoshikazu Miyanaga, Norinobu Yoshida
    A Design of Analog C-Matrix Circuits Used for Signal/Data Processing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:355-359 [Conf]
    
13. Qi Zhu, Noriyuki Ohtsuki, Yoshikazu Miyanaga, Norinobu Yoshida
    Noise-Robust Speech Analysis Using Running Spectrum Filtering. [Citation Graph (0, 0)][DBLP]
    IEICE Transactions, 2005, v:88, n:2, pp:541-548 [Journal]
    
14. Kazuma Fujioka, Noboru Hayasaka, Yoshikazu Miyanaga, Norinobu Yoshida
    Noise reduction of speech signals by running spectrum filtering. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2006, v:37, n:14, pp:52-61 [Journal]
    
15. Takayuki Sugawara, Shingo Yoshizawa, Yoshikazu Miyanaga
    Dynamic Reconfigurable Architecture for a Low-Power Despreader in VSF-OFCDM Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2287-2290 [Conf]
    
16. Shingo Yoshizawa, Yoshikazu Miyanaga
    Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3175-3178 [Conf]
    
17. Naoya Wada, Noboru Hayasaka, Shingo Yoshizawa, Yoshikazu Miyanaga
    Direct control on modulation spectrum for noise-robust speech recognition and spectral subtraction. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
18. Shingo Yoshizawa, Yoshikazu Miyanaga
    Tunable word length architecture for low power wireless OFDM demodulator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
19. Noboru Hayasaka, Yoshikazu Miyanaga
    Spectrum filtering with FRM for robust speech recognition. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
20. S. Yoshizawa, Y. Miyanaga, H. Ochi, Y. Itho, N. Hataoka, B. Sai, N. Takayama, M. Hirata
    300-Mbps OFDM baseband transceiver for wireless LAN systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
21. 
    A complete pipelined MMSE detection architecture in a 4x4 MIMO-OFDM receiver. [Citation Graph (, )][DBLP]
    
    
22. 
    Reconfigurable two-dimensional pipeline FFT processor in OFDM cognitive radio systems. [Citation Graph (, )][DBLP]
    
    
23. 
    FMO slice group maps using spatial and temporal indicators for H.264 wireless video transmission. [Citation Graph (, )][DBLP]
    
    
24. 
    VLSI Implementation of a 600-Mbps MIMO-OFDM Wireless Communication System. [Citation Graph (, )][DBLP]