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Stephen A. Szygenda: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Cheng-I Chuang, Stephen A. Szygenda, James D. Baker
    The automatic element routine generator: an automatic programming tool for functional simulator design. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 1992, pp:84-90 [Conf]
  2. Youngmin Hur, Stephen A. Szygenda
    Special purpose array processor for digital logic simulation. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 1995, pp:297-302 [Conf]
  3. Youngmin Hur, Stephen A. Szygenda
    A Simulation Tool for Design Error Models Utilizing Error Compression and Sampling. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 1996, pp:212-220 [Conf]
  4. Youngmin Hur, Saghir A. Shaikh, Silvian Goldenberg, D. Kacprzak, Stephen A. Szygenda
    Concurrent Fault and Design Error Simulation in Interactive Simulation Automation System. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 1997, pp:168-176 [Conf]
  5. Saghir A. Shaikh, Stephen A. Szygenda
    Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 1997, pp:64-0 [Conf]
  6. Sungho Kang, Stephen A. Szygenda
    Automatic VHDL Model Generation System. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:353-360 [Conf]
  7. Charles Wiley, A. T. Campbell III, Stephen A. Szygenda, Donald S. Fussell, Fred Hudson
    Multiresolution BSP Trees Applied to Terrain, Transparency, and General Objects. [Citation Graph (0, 0)][DBLP]
    Graphics Interface, 1997, pp:88-96 [Conf]
  8. Youngmin Hur, Stephen A. Szygenda, E. Scott Fehr, Granville E. Ott, Sungho Kang
    Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:340-347 [Conf]
  9. Brian Grayson, Saghir A. Shaikh, Stephen A. Szygenda
    Statistics on concurrent fault and design error simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:622-627 [Conf]
  10. Sungho Kang, Stephen A. Szygenda
    Modeling and Simulation of Design Errors. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:443-446 [Conf]
  11. N. Billawala, Stephen A. Szygenda, Ewald W. Thomson
    A Data Structure and Drive Mechanism for a Table-Driven Simulation System Employing Multilevel Structural Representations of Digital Systems. [Citation Graph (0, 0)][DBLP]
    ICSE, 1976, pp:151-157 [Conf]
  12. Asad Karim, Stephen A. Szygenda
    SMARTGEN: The Implementation of an Expert System for the Generation of Digital Logic Diagnostic Tests. [Citation Graph (0, 0)][DBLP]
    IEA/AIE (Vol. 1), 1988, pp:355-360 [Conf]
  13. John M. Hemphill, Stephen A. Szygenda
    Deriving Design Guidelines for Diagnosable Computer Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:131-135 [Conf]
  14. Ralph Marczynski, Mitchell A. Thornton, Stephen A. Szygenda
    Test vector generation and classification using FSM traversals. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:309-312 [Conf]
  15. Charles Wiley, K. M. Lau, Stephen A. Szygenda
    m3D: A Multidimensional Dynamic Configurable Router. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1857-1860 [Conf]
  16. Lun Li, Mitchell A. Thornton, Stephen A. Szygenda
    A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:32-38 [Conf]
  17. Saghir A. Shaikh, Silvian Goldenberg, Stephen A. Szygenda
    CON2FERS: A Concurrent Concurrent Fault and Design Error Simulator. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1996, pp:109-112 [Conf]
  18. Jin-Hyeung Kong, Stephen A. Szygenda
    MixMOS: a mixed-level simulator for digital MOS circuits using a new algebraic approach. [Citation Graph (0, 0)][DBLP]
    Computer-Aided Design, 1990, v:22, n:10, pp:618-632 [Journal]
  19. Sungho Kang, Stephen A. Szygenda
    Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1994, v:11, n:1, pp:18-26 [Journal]
  20. Stephen A. Szygenda, Edward W. Thomson
    Modeling and Digital Simulation for Design Verification and Diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:12, pp:1242-1253 [Journal]
  21. Sungho Kang, Stephen A. Szygenda
    The simulation automation system (SAS); concepts, implementation, and results. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:89-99 [Journal]

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