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Wonyong Sung :
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Jae-Woo Ahn , Soo-Mook Moon , Wonyong Sung An Efficient Compiled Simulation System for VLIW Code Verification. [Citation Graph (0, 0)][DBLP ] Annual Simulation Symposium, 1998, pp:91-0 [Conf ] Yongjoo Kim , Kyuseok Kim , Youngsoo Shin , Taekyoon Ahn , Wonyong Sung , Kiyoung Choi , Soonhoi Ha An integrated hardware-software cosimulation environment for heterogeneous systems prototyping. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 1995, pp:- [Conf ] Wonyong Sung , Soonhoi Ha A Hardware Software Cosimulation Backplane with Automatic Interface Generation. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 1998, pp:177-182 [Conf ] Wonyong Sung , Soonhoi Ha Optimized Timed Hardware Software Cosimulation without Roll-back. [Citation Graph (0, 0)][DBLP ] DATE, 1998, pp:945-946 [Conf ] Jong-bok Lee , Wonyong Sung , Soo-Mook Moon An Enhanced Two-Level Adaptive Multiple Branch Prediction for Superscalar Processors. [Citation Graph (0, 0)][DBLP ] Euro-Par, 1997, pp:1053-1060 [Conf ] Wonyong Sung , Byonghyo Shim Adaptive Threshold Error Diffusion Technique for Color Inkjet Printing . [Citation Graph (0, 0)][DBLP ] ICIP (1), 1997, pp:779-782 [Conf ] Hoseok Chang , Wonchul Lee , Wonyong Sung Optimization of power consumption for an ARM7-based multimedia handheld device. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2003, pp:105-108 [Conf ] Moonseok Kang , Wonyong Sung Memory access overhead reduction for a digital color copier implementation using a VLIW digital signal processor. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 2005, pp:1465-1468 [Conf ] Jae-Woo Ahn , Soo-Mook Moon , Wonyong Sung Feedback-directed memory disambiguation for embedded multimedia VLIW computing. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 2001, pp:461-464 [Conf ] Jongseo Sohn , Suhong Ryu , Wonyong Sung A codebook shaping method for perceptual quality improvement of CELP coders. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 2001, pp:357-360 [Conf ] Wonyong Sung , Junedong Kim , Soonhoi Ha Memory Efficient Software Synthesis from Dataflow Graph. [Citation Graph (0, 0)][DBLP ] ISSS, 1998, pp:137-144 [Conf ] Sangduck Park , Hyunjin Lim , Hoseok Chang , Wonyong Sung Compressed Swapping for NAND Flash Memory Based Embedded Systems. [Citation Graph (0, 0)][DBLP ] SAMOS, 2005, pp:314-323 [Conf ] Ki-Il Kum , Wonyong Sung Combined word-length optimization and high-level synthesis ofdigital signal processing systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:921-930 [Journal ] Jae-Woo Ahn , Wonyong Sung Multimedia processor-based implementation of an error-diffusion halftoning algorithm exploiting subword parallelism. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Circuits Syst. Video Techn., 2001, v:11, n:2, pp:129-138 [Journal ] Wonyong Sung , Sanjit K. Mitra , Branko Jeren Multiprocessor Implementation of Digital Filtering Algorithms Using a Parallel Block Processing Method. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Parallel Distrib. Syst., 1992, v:3, n:1, pp:110-120 [Journal ] Hyojin Choi , Wonchul Lee , Wonyong Sung Memory Access Reduced Software Implementation of H.264/AVC Sub-pixel Motion Estimation Using Differential Data Encoding. [Citation Graph (0, 0)][DBLP ] ISCAS, 2007, pp:2898-2901 [Conf ] Junho Cho , Hoseok Chang , Wonyong Sung An FPGA based SIMD processor with a vector memory unit. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Wonyong Sung , Soonhoi Ha Memory efficient software synthesis with mixed coding style from dataflow graphs. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:522-526 [Journal ] Efficient vectorization of SIMD programs with non-aligned and irregular data access hardware. [Citation Graph (, )][DBLP ] Scalable HMM based inference engine in large vocabulary continuous speech recognition. [Citation Graph (, )][DBLP ] Software implementation of Chien search process for strong BCH codes. [Citation Graph (, )][DBLP ] Software optimization of MPEG audio layer-III for a 32 bit RISC processor. [Citation Graph (, )][DBLP ] Fast Block Mode Decision for H.264/AVC on a Programmable Digital Signal Processor. [Citation Graph (, )][DBLP ] Performance Optimization of a Multimedia Player on a Mobile CPU Platform. [Citation Graph (, )][DBLP ] Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories. [Citation Graph (, )][DBLP ] Performance Evaluation of an SIMD Architecture with a Multi-bank Vector Memory Unit. [Citation Graph (, )][DBLP ] Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard. [Citation Graph (, )][DBLP ] SIMD processor based implementation of recursive filtering equations. [Citation Graph (, )][DBLP ] Massively parallel implementation of cyclic LDPC codes on a general purpose graphics processing unit. [Citation Graph (, )][DBLP ] VLSI for 5000-word continuous speech recognition. [Citation Graph (, )][DBLP ] OpenMP-based parallel implementation of a continuous speech recognizer on a multi-core system. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.331secs