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Roger D. Chamberlain: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Roger D. Chamberlain, Eric Hemmeter, Robert Morley, Jason White
    Modeling the Power Consumption of Audio Signal Processing Computations Using Customized Numerical Representations. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 2003, pp:249-255 [Conf]
  2. Roger D. Chamberlain, Ch'ng Shi Baw, Mark A. Franklin, Christopher Hackmann, Praveen Krishnamurthy, Abhijit Mahajan, Michael Wrighton
    Evaluating the Performance of Photonic Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 2002, pp:209-218 [Conf]
  3. Jason E. Fritts, Roger D. Chamberlain
    Breaking the Memory Bottleneck with an Optical Data Path. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 2002, pp:352-0 [Conf]
  4. Praveen Krishnamurthy, Mark A. Franklin, Roger D. Chamberlain
    Dynamic Reconfiguration of an Optical Interconnect. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 2003, pp:89-97 [Conf]
  5. Bradley L. Noble, J. Cris Wade, Roger D. Chamberlain
    Performance Predictions for Speculative, Synchronous, VLSI Logic Simulation. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 2001, pp:56-64 [Conf]
  6. Roger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy
    Optical Network Reconfiguration for Signal Processing Applications. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:344-0 [Conf]
  7. Michael D. DeVore, Roger D. Chamberlain, George Engel, Joseph A. O'Sullivan, Mark A. Franklin
    Tradeoffs Between Quality of Results and Resource Consumption in a Recognition System. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:391-0 [Conf]
  8. Praveen Krishnamurthy, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Kwame Gyang, Joseph M. Lancaster
    Biosequence Similarity Search on the Mercury System. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:365-375 [Conf]
  9. Roger D. Chamberlain
    Parallel Logic Simulation of VLSI Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:139-143 [Conf]
  10. Kenneth F. Wong, Mark A. Franklin, Roger D. Chamberlain, B. L. Shing
    Statistics on logic simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:13-19 [Conf]
  11. Arpith C. Jacob, Brandon Harris, Jeremy Buhler, Roger D. Chamberlain, Young H. Cho
    Scalable Softcore Vector Processor for Biosequence Applications. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:295-296 [Conf]
  12. Roger D. Chamberlain, Gregory D. Peterson, Mark A. Franklin, Michael A. Province
    Genetic epidemiology, parallel algorithms, and workstation networks. [Citation Graph (0, 0)][DBLP]
    HICSS (5), 1995, pp:101-111 [Conf]
  13. Bradley L. Noble, Roger D. Chamberlain
    Performance Model for Speculative Simulation using Predictive Optimism. [Citation Graph (0, 0)][DBLP]
    HICSS, 1999, pp:- [Conf]
  14. Bradley L. Noble, Gregory D. Peterson, Roger D. Chamberlain
    Performance of synchronous parallel discrete-event simulation. [Citation Graph (0, 0)][DBLP]
    HICSS (2), 1995, pp:185-186 [Conf]
  15. Gregory D. Peterson, Roger D. Chamberlain
    Stealing cycles: Can we get along? [Citation Graph (0, 0)][DBLP]
    HICSS (2), 1995, pp:422-441 [Conf]
  16. Mark A. Franklin, Roger D. Chamberlain, Michael Henrichs, Berkley Shands, Jason White
    An Architecture for Fast Processing of Large Unstructured Data Sets. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:280-287 [Conf]
  17. Gregory D. Peterson, Roger D. Chamberlain
    Performance of a Globally-Clocked Parallel Simulator. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:289-298 [Conf]
  18. Ellen E. Witte, Roger D. Chamberlain, Mark A. Franklin
    Parallel Simulated Annealing Using Speculative Computation. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1990, pp:286-290 [Conf]
  19. Rahul P. Maddimsetty, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Brandon Harris
    Accelerator design for protein sequence HMM search. [Citation Graph (0, 0)][DBLP]
    ICS, 2006, pp:288-296 [Conf]
  20. Roger D. Chamberlain, Mark A. Franklin
    Analysis of Parallel Mixed-Mode Simulation Algorithms. [Citation Graph (0, 0)][DBLP]
    IPPS, 1991, pp:155-160 [Conf]
  21. Qiong Zhang, Roger D. Chamberlain, Ronald S. Indeck, Benjamin M. West, Jason White
    Massively Parallel Data Mining Using Reconfigurable Hardware: Approximate String Matching. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  22. Shobana Padmanabhan, Ron K. Cytron, Roger D. Chamberlain, John W. Lockwood
    Automatic application-specific microarchitecture reconfiguration. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  23. Roger D. Chamberlain, Ron K. Cytron, Jason E. Fritts, John W. Lockwood
    Vision for liquid architecture. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  24. Gary Stiehr, Roger D. Chamberlain
    Improving cluster utilization through intelligent processor sharing. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  25. Ch'ng Shi Baw, Roger D. Chamberlain, Mark A. Franklin
    Fair Scheduling in an Optical Interconnection Network. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 1999, pp:56-0 [Conf]
  26. Roger D. Chamberlain, John W. Lockwood, Saurabh Gayen, Richard Hough, Phillip Jones
    Use of a Soft-Core Processor in a Hardware/Software Codesign Laboratory. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:97-98 [Conf]
  27. Bradley L. Noble, Roger D. Chamberlain
    Analytic performance model for speculative, synchronous, discrete-event simulation. [Citation Graph (0, 0)][DBLP]
    PADS, 2000, pp:30-44 [Conf]
  28. Roger D. Chamberlain, Mark A. Franklin
    Performance Effects of Synchronization in Parallel Processors. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:611-616 [Conf]
  29. Gregory D. Peterson, Roger D. Chamberlain
    Exploiting lookahead in synchronous parallel simulation. [Citation Graph (0, 0)][DBLP]
    Winter Simulation Conference, 1993, pp:706-712 [Conf]
  30. Mary L. Bailey, Jack V. Briner Jr., Roger D. Chamberlain
    Parallel Logic Simulation of VLSI Systems. [Citation Graph (0, 0)][DBLP]
    ACM Comput. Surv., 1994, v:26, n:3, pp:255-294 [Journal]
  31. Gregory D. Peterson, Roger D. Chamberlain
    Parallel application performance in a shared resource environment. [Citation Graph (0, 0)][DBLP]
    Distributed Systems Engineering, 1996, v:3, n:1, pp:9-19 [Journal]
  32. Shobana Padmanabhan, Phillip Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger D. Chamberlain, Ron Cytron, Jason E. Fritts, John W. Lockwood
    Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2005, v:33, n:2-3, pp:115-136 [Journal]
  33. George Varghese, Roger D. Chamberlain, William E. Weihl
    Deriving Global Virtual Time Algorithms from Conservative Simulation Protocols. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1995, v:54, n:2, pp:121-126 [Journal]
  34. Roger D. Chamberlain, Mark A. Franklin
    Collecting Data About Logic Simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:3, pp:405-412 [Journal]
  35. Roger D. Chamberlain, Mark A. Franklin, Ch'ng Shi Baw
    Gemini: An Optical Interconnection Network for Parallel Processing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2002, v:13, n:10, pp:1038-1055 [Journal]
  36. Ellen E. Witte, Roger D. Chamberlain, Mark A. Franklin
    Parallel Simulated Annealing using Speculative Computation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1991, v:2, n:4, pp:483-494 [Journal]
  37. Roger D. Chamberlain, Mark A. Franklin, Abhijit Mahajan
    VLSI Photonic Ring Interconnect for Embedded Multicomputers: Architecture and Performance. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2001, pp:351-358 [Conf]
  38. Arpith C. Jacob, Joseph M. Lancaster, Jeremy D. Buhler, Roger D. Chamberlain
    Preliminary results in accelerating profile HMM search on FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  39. Saurabh Gayen, Eric J. Tyson, Mark A. Franklin, Roger D. Chamberlain
    A Federated Simulation Environment for Hybrid Systems. [Citation Graph (0, 0)][DBLP]
    PADS, 2007, pp:198-210 [Conf]

  40. Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs. [Citation Graph (, )][DBLP]


  41. FPGA-accelerated seed generation in Mercury BLASTP. [Citation Graph (, )][DBLP]


  42. Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only). [Citation Graph (, )][DBLP]


  43. A Banded Smith-Waterman FPGA Accelerator for Mercury BLASTP. [Citation Graph (, )][DBLP]


  44. Optimal runtime reconfiguration strategies for systolic arrays. [Citation Graph (, )][DBLP]


  45. Understanding the performance of streaming applications deployed on hybrid systems. [Citation Graph (, )][DBLP]


  46. Analytic performance models for bounded queueing systems. [Citation Graph (, )][DBLP]


  47. Poster abstract: Reliable data collection from mobile users for real-time clinical monitoring. [Citation Graph (, )][DBLP]


  48. Application-guided tool development for architecturally diverse computation. [Citation Graph (, )][DBLP]


  49. Application development on hybrid systems. [Citation Graph (, )][DBLP]


  50. Sorting on architecturally diverse computer systems. [Citation Graph (, )][DBLP]


  51. Deadlock avoidance for streaming computations with filtering. [Citation Graph (, )][DBLP]


  52. Empirical performance assessment using soft-core processors on reconfigurable hardware. [Citation Graph (, )][DBLP]


  53. Auto-Pipe: Streaming Applications on Architecturally Diverse Systems. [Citation Graph (, )][DBLP]


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