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Mark A. Franklin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mark A. Franklin, G. Scott Graham, Ram K. Gupta
    Anomalies with Variable Partition Paging Algorithms. [Citation Graph (1, 0)][DBLP]
    Commun. ACM, 1978, v:21, n:3, pp:232-236 [Journal]
  2. Roger D. Chamberlain, Ch'ng Shi Baw, Mark A. Franklin, Christopher Hackmann, Praveen Krishnamurthy, Abhijit Mahajan, Michael Wrighton
    Evaluating the Performance of Photonic Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 2002, pp:209-218 [Conf]
  3. Praveen Krishnamurthy, Mark A. Franklin, Roger D. Chamberlain
    Dynamic Reconfiguration of an Optical Interconnect. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 2003, pp:89-97 [Conf]
  4. Tilman Wolf, Mark A. Franklin
    Design Tradeoffs for Embedded Network Processors. [Citation Graph (0, 0)][DBLP]
    ARCS, 2002, pp:149-164 [Conf]
  5. Roger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy
    Optical Network Reconfiguration for Signal Processing Applications. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:344-0 [Conf]
  6. Michael D. DeVore, Roger D. Chamberlain, George Engel, Joseph A. O'Sullivan, Mark A. Franklin
    Tradeoffs Between Quality of Results and Resource Consumption in a Recognition System. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:391-0 [Conf]
  7. Praveen Krishnamurthy, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Kwame Gyang, Joseph M. Lancaster
    Biosequence Similarity Search on the Mercury System. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:365-375 [Conf]
  8. Chia-Hsing Chien, Mark A. Franklin, Tienyo Pan, Prithvi Prabhu
    ARAS: asynchronous RISC architecture simulator. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1995, pp:210-0 [Conf]
  9. Michela Becchi, Mark A. Franklin, Patrick Crowley
    Performance/area efficiency in chip multiprocessors with micro-caches. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2007, pp:247-258 [Conf]
  10. Kenneth F. Wong, Mark A. Franklin, Roger D. Chamberlain, B. L. Shing
    Statistics on logic simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:13-19 [Conf]
  11. Mark A. Franklin, Prithvi Prabhu
    Performance Optimization of Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:374-379 [Conf]
  12. Roger D. Chamberlain, Gregory D. Peterson, Mark A. Franklin, Michael A. Province
    Genetic epidemiology, parallel algorithms, and workstation networks. [Citation Graph (0, 0)][DBLP]
    HICSS (5), 1995, pp:101-111 [Conf]
  13. Kenneth F. Wong, Mark A. Franklin
    Distributed Computing Systems and Checkpointing. [Citation Graph (0, 0)][DBLP]
    HPDC, 1993, pp:224-233 [Conf]
  14. Mark A. Franklin, Roger D. Chamberlain, Michael Henrichs, Berkley Shands, Jason White
    An Architecture for Fast Processing of Large Unstructured Data Sets. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:280-287 [Conf]
  15. Sanjay Dhar, Mark A. Franklin, Donald F. Wann
    Timing Control of VLSI Based NlogN and Crossbar Networks. [Citation Graph (0, 0)][DBLP]
    ICPP, 1983, pp:59-64 [Conf]
  16. Mark A. Franklin, Sanjay Dhar
    On Designing Interconnection Networks for Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:208-215 [Conf]
  17. Vasudha Govindan, Mark A. Franklin
    Speculative Computation: Overcoming Communication Delays. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1994, pp:12-16 [Conf]
  18. Ellen E. Witte, Roger D. Chamberlain, Mark A. Franklin
    Parallel Simulated Annealing Using Speculative Computation. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1990, pp:286-290 [Conf]
  19. Stefan Hendrata, Mark A. Franklin
    Performance Comparison of Parallel Finite Element and Monte Carlo Methods in Optical Tomography. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2001, pp:51-58 [Conf]
  20. Rahul P. Maddimsetty, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Brandon Harris
    Accelerator design for protein sequence HMM search. [Citation Graph (0, 0)][DBLP]
    ICS, 2006, pp:288-296 [Conf]
  21. Roger D. Chamberlain, Mark A. Franklin
    Analysis of Parallel Mixed-Mode Simulation Algorithms. [Citation Graph (0, 0)][DBLP]
    IPPS, 1991, pp:155-160 [Conf]
  22. Vasudha Govindan, Mark A. Franklin
    Effect of Control Parameters on Dynamic Load Balancing. [Citation Graph (0, 0)][DBLP]
    IPPS, 1994, pp:452-460 [Conf]
  23. Vasudha Govindan, Mark A. Franklin
    Application Load Imbalance on Parallel Processors. [Citation Graph (0, 0)][DBLP]
    IPPS, 1996, pp:836-842 [Conf]
  24. Mark A. Franklin, Eric J. Tyson, J. Buckley, Patrick Crowley, John Maschmeyer
    Auto-pipe and the X language: a pipeline design tool and description language. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  25. Mark A. Franklin, S. A. Kahn, M. J. Stucki
    Design Issues in the Development of a Modular Mutliprocessor Communications Network. [Citation Graph (0, 0)][DBLP]
    ISCA, 1979, pp:182-187 [Conf]
  26. Mark A. Franklin, Donald F. Wann
    Asynchronous and clocked control structures for VLSI based interconnection networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 1982, pp:50-59 [Conf]
  27. Kenneth F. Wong, Mark A. Franklin
    Performance Analysis and Design of a Logic Simulation Machine. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:46-55 [Conf]
  28. Ch'ng Shi Baw, Roger D. Chamberlain, Mark A. Franklin
    Fair Scheduling in an Optical Interconnection Network. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 1999, pp:56-0 [Conf]
  29. Mark A. Franklin, Vinayak Joshi
    SimplePipe: A Simulation Tool for Task Allocation and Design of Processor Pipelines with Application to Network Processors. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 2004, pp:59-66 [Conf]
  30. Mark A. Franklin, Tienyo Pan
    Clocked and asynchronous instruction pipelines. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:177-184 [Conf]
  31. Roger D. Chamberlain, Mark A. Franklin
    Performance Effects of Synchronization in Parallel Processors. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:611-616 [Conf]
  32. Mark A. Franklin, Ram K. Gupta
    Computation of Page Fault Probability from Program Transition Diagram. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 1974, v:17, n:4, pp:186-191 [Journal]
  33. Tilman Wolf, Prashanth Pappu, Mark A. Franklin
    Predictive scheduling of network processors. [Citation Graph (0, 0)][DBLP]
    Computer Networks, 2003, v:41, n:5, pp:601-621 [Journal]
  34. Mark A. Franklin, Sanjay Dhar
    Interconnection Networks: Physical Design and Performance Analysis. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1986, v:3, n:3, pp:352-372 [Journal]
  35. Ken Wong, Mark A. Franklin
    Performance Analysis of a Parallel Logic Simulation Machine. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1989, v:7, n:3, pp:416-440 [Journal]
  36. Kenneth F. Wong, Mark A. Franklin
    Checkpointing in Distributed Computing Systems. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1996, v:35, n:1, pp:67-75 [Journal]
  37. Mark A. Franklin, Vasudha Govindan
    A General Matrix Iterative Model for Dynamic Load Balancing. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1996, v:22, n:7, pp:969-989 [Journal]
  38. Robert P. Bogott, Mark A. Franklin
    Evaluation of Markov Program Models in Virtual Memory Systems. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1975, v:5, n:4, pp:337-346 [Journal]
  39. Mark A. Franklin
    Parallel Solution of Ordinary Differential Equations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:5, pp:413-420 [Journal]
  40. Mark A. Franklin
    VLSI Performance Comparison of Banyan and Crossbar Communications Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:4, pp:283-291 [Journal]
  41. Mark A. Franklin, Norman L. Soong
    One-Dimensional Optimization on Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:1, pp:61-66 [Journal]
  42. Mark A. Franklin, Donald F. Wann, William J. Thomas
    Pin Limitations and Partitioning of VLSI Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:11, pp:1109-1116 [Journal]
  43. Ram K. Gupta, Mark A. Franklin
    Working Set and Page Fault Frequency Paging Algorithms: A Performance Comparison. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:8, pp:706-712 [Journal]
  44. Donald F. Wann, Mark A. Franklin
    Asynchronous and Clocked Control Structures for VSLI Based Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:3, pp:284-293 [Journal]
  45. Roger D. Chamberlain, Mark A. Franklin
    Collecting Data About Logic Simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:3, pp:405-412 [Journal]
  46. Roger D. Chamberlain, Mark A. Franklin, Ch'ng Shi Baw
    Gemini: An Optical Interconnection Network for Parallel Processing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2002, v:13, n:10, pp:1038-1055 [Journal]
  47. Ellen E. Witte, Roger D. Chamberlain, Mark A. Franklin
    Parallel Simulated Annealing using Speculative Computation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1991, v:2, n:4, pp:483-494 [Journal]
  48. Tilman Wolf, Mark A. Franklin
    Performance Models for Network Processor Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2006, v:17, n:6, pp:548-561 [Journal]
  49. Roger D. Chamberlain, Mark A. Franklin, Abhijit Mahajan
    VLSI Photonic Ring Interconnect for Embedded Multicomputers: Architecture and Performance. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2001, pp:351-358 [Conf]
  50. Saurabh Gayen, Eric J. Tyson, Mark A. Franklin, Roger D. Chamberlain
    A Federated Simulation Environment for Hybrid Systems. [Citation Graph (0, 0)][DBLP]
    PADS, 2007, pp:198-210 [Conf]

  51. Application-guided tool development for architecturally diverse computation. [Citation Graph (, )][DBLP]


  52. Application development on hybrid systems. [Citation Graph (, )][DBLP]


  53. A workload for evaluating deep packet inspection architectures. [Citation Graph (, )][DBLP]


  54. Auto-Pipe: Streaming Applications on Architecturally Diverse Systems. [Citation Graph (, )][DBLP]


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