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Title:
Author:
José A. B. Fortes: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zina Ben-Miled, José A. B. Fortes, Rudolf Eigenmann, Valerie E. Taylor
    Towards the Design of a Heterogeneous Hierarchical Machine: A Simulation Approach. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 1997, pp:126-136 [Conf]
  2. José A. B. Fortes
    Nanocomputing with Delays. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:3-0 [Conf]
  3. Jie Han, Erin Taylor, Jianbo Gao, José A. B. Fortes
    Faults, Error Bounds and Reliability of Nanoelectronic Circuits. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:247-253 [Conf]
  4. Hyuk-Jae Lee, José A. B. Fortes
    Data Alignments for Modular Time-Space Mappings of BLAS-like Algorithms. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:34-0 [Conf]
  5. Hyuk-Jae Lee, José A. B. Fortes
    Automatic Generation of Modular Mappings. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:155-164 [Conf]
  6. Weijia Shang, Matthew T. O'Keefe, José A. B. Fortes
    Generalized cycle shrinking. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:131-144 [Conf]
  7. Josep Llosa, Mateo Valero, José A. B. Fortes, Eduard Ayguadé
    Using Sacks to Organize Registers in VLIW Machines. [Citation Graph (0, 0)][DBLP]
    CONPAR, 1994, pp:628-639 [Conf]
  8. José A. B. Fortes
    Case Study: Transnational Digital Government Research - Building Regional Partnerships. [Citation Graph (0, 0)][DBLP]
    DG.O, 2003, pp:- [Conf]
  9. José A. B. Fortes
    Transnational Digital Government Research: Project Highlights. [Citation Graph (0, 0)][DBLP]
    DG.O, 2004, pp:- [Conf]
  10. José A. B. Fortes
    Transnational digital government research project highlights. [Citation Graph (0, 0)][DBLP]
    DG.O, 2005, pp:171-172 [Conf]
  11. Andréa M. Matsunaga, Maurício O. Tsugawa, José A. B. Fortes
    Virtual machines in transnational digital government: a case study. [Citation Graph (0, 0)][DBLP]
    DG.O, 2005, pp:255-256 [Conf]
  12. S. Su, José A. B. Fortes, T. R. Kasad, M. Patil, Andréa M. Matsunaga, Maurício O. Tsugawa, Violetta Cavalli-Sforza, Jaime G. Carbonell, Peter J. Jansen, W. Ward, R. Cole, Donald F. Towsley, Weifeng Chen, Annie I. Antón, Qingfeng He, C. McSweeney, L. deBrens, J. Ventura, P. Taveras, R. Connolly, C. Ortega, B. Piñeres, O. Brooks, M. Herrera
    A Prototype System for Transnational Information Sharing and Process Coordination. [Citation Graph (0, 0)][DBLP]
    DG.O, 2004, pp:- [Conf]
  13. S. Su, José A. B. Fortes, T. R. Kasad, M. Patil, Andréa M. Matsunaga, Maurício O. Tsugawa, Violetta Cavalli-Sforza, Jaime G. Carbonell, Peter J. Jansen, W. Ward, R. Cole, Donald F. Towsley, Weifeng Chen, Annie I. Antón, Qingfeng He, C. McSweeney, L. deBrens, J. Ventura, P. Taveras, R. Connolly, C. Ortega, B. Piñeres, O. Brooks, M. Herrera
    A Prototype System for Transnational Information Sharing and Process Coordination: System Demo. [Citation Graph (0, 0)][DBLP]
    DG.O, 2004, pp:- [Conf]
  14. Maurício O. Tsugawa, Andréa M. Matsunaga, José A. B. Fortes
    Virtualization technologies in transnational DG. [Citation Graph (0, 0)][DBLP]
    DG.O, 2006, pp:456-457 [Conf]
  15. Andréa M. Matsunaga, Maurício O. Tsugawa, José A. B. Fortes
    Integration of text-based applications into service-oriented architectures for transnational digital government. [Citation Graph (0, 0)][DBLP]
    DG.O, 2007, pp:112-121 [Conf]
  16. Liping Zhu, Andréa M. Matsunaga, Vivekananthan Sanjeepan, Herman Lam, José A. B. Fortes
    Application Modeling and Representation for Automatic Grid-Enabling of Legacy Applications. [Citation Graph (0, 0)][DBLP]
    e-Science, 2005, pp:24-31 [Conf]
  17. Andréa M. Matsunaga, Maurício O. Tsugawa, Ming Zhao, Liping Zhu, Vivekananthan Sanjeepan, Sumalatha Adabala, Renato J. O. Figueiredo, Herman Lam, José A. B. Fortes
    On the Use of Virtualization and Service Technologies to Enable Grid-Computing. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2005, pp:1-12 [Conf]
  18. Rajesh Subramanyan, José Miguel-Alonso, José A. B. Fortes
    A Reconfigurable Monitoring System for Large-Scale Network Computing. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2003, pp:98-108 [Conf]
  19. José A. B. Fortes, M. Arif Samad
    DEFT: A Design for Testability Expert System. [Citation Graph (0, 0)][DBLP]
    FJCC, 1986, pp:899-908 [Conf]
  20. Zina Ben-Miled, José A. B. Fortes, Rudolf Eigenmann, Valerie E. Taylor
    On the Implementation of Broadcast, Scatter and Gather in a Heterogeneous Architecture. [Citation Graph (0, 0)][DBLP]
    HICSS (3), 1998, pp:216-225 [Conf]
  21. Jordi Cortadella, José A. B. Fortes, Edward A. Lee
    Design and Prototyping of Digital Signal Processing (DSP) Systems: Introduction. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:56-57 [Conf]
  22. Renato J. O. Figueiredo, José A. B. Fortes
    Impact of Heterogeneity on DSM Performance. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:26-0 [Conf]
  23. Sumalatha Adabala, Nirav H. Kapadia, José A. B. Fortes
    Interfacing Wide-Area Network Computing and Cluster Management Software: Condor, DQS and PBS via PUNCH. [Citation Graph (0, 0)][DBLP]
    HPDC, 2000, pp:306-307 [Conf]
  24. Renato J. O. Figueiredo, Nirav H. Kapadia, José A. B. Fortes
    The PUNCH Virtual File System: Seamless Access to Decentralized Storage Services in a Computational Grid. [Citation Graph (0, 0)][DBLP]
    HPDC, 2001, pp:334-0 [Conf]
  25. Nirav H. Kapadia, José A. B. Fortes
    On the Design of a Demand-Based Network-Computing System: The Purdue University Network-Computing Hub. [Citation Graph (0, 0)][DBLP]
    HPDC, 1998, pp:71-80 [Conf]
  26. Nirav H. Kapadia, José A. B. Fortes, Carla E. Brodley
    Predictive Application-Performance Modeling in a Computational Grid Environment. [Citation Graph (0, 0)][DBLP]
    HPDC, 1999, pp:- [Conf]
  27. Dolors Royo, Luis Díaz de Cerio, Nirav H. Kapadia, José A. B. Fortes
    Active Yellow Pages: A Pipelined Resource Management Architecture for Wide-Area Network Computing. [Citation Graph (0, 0)][DBLP]
    HPDC, 2001, pp:147-157 [Conf]
  28. Jing Xu, Sumalatha Adabala, José A. B. Fortes
    Towards Autonomic Virtual Applications in the In-VIGO System. [Citation Graph (0, 0)][DBLP]
    ICAC, 2005, pp:15-26 [Conf]
  29. José A. B. Fortes, Renato J. O. Figueiredo, Linda Hermer-Vazquez, José Carlos Príncipe, Justin C. Sanchez
    A New Architecture for Deriving Dynamic Brain-Machine Interfaces. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science (3), 2006, pp:546-553 [Conf]
  30. Renato J. O. Figueiredo, Peter A. Dinda, José A. B. Fortes
    A Case For Grid Computing On Virtual Machine. [Citation Graph (0, 0)][DBLP]
    ICDCS, 2003, pp:550-559 [Conf]
  31. Nirav H. Kapadia, José A. B. Fortes, Mark S. Lundstrom
    Statewide Enterprise Computing with the Purdue University Network-Computing Hubs. [Citation Graph (0, 0)][DBLP]
    ICEIS, 1999, pp:657-664 [Conf]
  32. Sumalatha Adabala, José A. B. Fortes
    An Online Heuristic for Data Placement in Computer Systems with Active Disks. [Citation Graph (0, 0)][DBLP]
    ICPP, 2002, pp:219-0 [Conf]
  33. James B. Armstrong, Howard Jay Siegel, William E. Cohen, Min Tan, Henry G. Dietz, José A. B. Fortes
    Dynamic Task Migration from SPMD to SIMD Virtual Machines. [Citation Graph (0, 0)][DBLP]
    ICPP, 1994, pp:160-169 [Conf]
  34. Hasan Cam, José A. B. Fortes
    Fault-Tolerant Self-Routing Permutation Networks. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1992, pp:243-247 [Conf]
  35. William W. Carlson, José A. B. Fortes
    On the Performance of Combined Data Flow and Control Flow Systems: Experiments Using Two Iterative Algorithms. [Citation Graph (0, 0)][DBLP]
    ICPP, 1987, pp:671-679 [Conf]
  36. Renato J. O. Figueiredo, José A. B. Fortes
    Hardware Support for Extracting Coarse-Grain Speculative Parallelism in Distributed Shared-Memory Multiprocesors. [Citation Graph (0, 0)][DBLP]
    ICPP, 2001, pp:214-226 [Conf]
  37. Nirav H. Kapadia, José A. B. Fortes
    Block-Row Sparse Matrix-Vector Multiplication on SIMD Machines. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1995, pp:34-41 [Conf]
  38. Hyuk-Jae Lee, José A. B. Fortes
    Conditions of Blocked BLAS-like Algorithms for Data Alignment and Communication Minimization. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1995, pp:220-223 [Conf]
  39. Hyuk-Jae Lee, José A. B. Fortes
    Automatic generation of injective modular mappings. [Citation Graph (0, 0)][DBLP]
    ICPP, 1997, pp:417-0 [Conf]
  40. Matthew T. O'Keefe, José A. B. Fortes
    A Comparative Study of Two Systematic Design Methodologies for Systolic Arrays. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:672-675 [Conf]
  41. Gene Saghi, Howard Jay Siegel, José A. B. Fortes
    On the Viability of a Quantitative Model of System Reconfiguration Due to a Fault. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1992, pp:233-242 [Conf]
  42. Gene Saghi, Howard Jay Siegel, José A. B. Fortes
    On the Practical Application of a Quantitative Model of System Reconfiguration Due to a Fault. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:248-252 [Conf]
  43. Hemal V. Shah, José A. B. Fortes
    Relaxation and Hybrid Approaches to Gröbner Basis Computation on Distributed Memory Machines. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1995, pp:68-75 [Conf]
  44. Hemal V. Shah, José A. B. Fortes
    Effects of Dynamic Task Distributions on the Performance of a Class of Irregular Computations. [Citation Graph (0, 0)][DBLP]
    ICPP, 1997, pp:242-0 [Conf]
  45. Weijia Shang, José A. B. Fortes
    Independent Partitioning of Algorithms With Uniform Data Dependencies. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1988, pp:26-33 [Conf]
  46. Weijia Shang, José A. B. Fortes
    Time-Optimal and Conflict-Free Mappings of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1990, pp:101-110 [Conf]
  47. Weijia Shang, Matthew T. O'Keefe, José A. B. Fortes
    On Loop Transformations for Generalized Cycle Shrinking. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1991, pp:132-141 [Conf]
  48. Wessam Hassanein, José A. B. Fortes, Rudolf Eigenmann
    Data forwarding through in-memory precomputation threads. [Citation Graph (0, 0)][DBLP]
    ICS, 2004, pp:207-216 [Conf]
  49. Hyuk-Jae Lee, James P. Robertson, José A. B. Fortes
    Generalized Cannon's Algorithm for Parallel Matrix Multiplication. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:44-51 [Conf]
  50. Vivekananthan Sanjeepan, Andréa M. Matsunaga, Liping Zhu, Herman Lam, José A. B. Fortes
    A Service-Oriented, Scalable Approach to Grid-Enabling of Legacy Scientific Applications. [Citation Graph (0, 0)][DBLP]
    ICWS, 2005, pp:553-560 [Conf]
  51. Sumalatha Adabala, Andréa M. Matsunaga, Maurício O. Tsugawa, Renato J. O. Figueiredo, José A. B. Fortes
    Single Sign-On in In-VIGO: Role-Based Access via Delegation Mechanisms Using Short-Lived User Identities. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  52. Ali Raza Butt, Sumalatha Adabala, Nirav H. Kapadia, Renato J. O. Figueiredo, José A. B. Fortes
    Fine-Grain Access Control for Securing Shared Resources in Computational Grids. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  53. Nirav H. Kapadia, Renato J. O. Figueiredo, José A. B. Fortes
    Enhancing the Scalability and Usability of Computational Grids via Logical User Accounts and Virtual. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:82- [Conf]
  54. Hyuk-Jae Lee, José A. B. Fortes
    Toward data distribution independent parallel matrix multiplication. [Citation Graph (0, 0)][DBLP]
    IPPS, 1995, pp:436-440 [Conf]
  55. Zhenhui Yang, Weijia Shang, José A. B. Fortes
    Conflict-Free Scheduling of Nested Loop Algorithms on Lower Dimensional Processor Arrays. [Citation Graph (0, 0)][DBLP]
    IPPS, 1992, pp:156-164 [Conf]
  56. J. Fortes
    HCW panel: programming heterogeneous systems - Less pain! Better performance! [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  57. Maurício O. Tsugawa, José A. B. Fortes
    A virtual network (ViNe) architecture for grid computing. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  58. José A. B. Fortes, Dan I. Moldovan
    Data Broadcasting in Linearly Scheduled Array Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1984, pp:224-231 [Conf]
  59. Darwen Rau, José A. B. Fortes, Howard Jay Siegel
    Destination Tag Routing Techniques Based on a State Model for the IADM Network. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:318-324 [Conf]
  60. José A. B. Fortes
    Future Challenges in VLSI Design. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:5-7 [Conf]
  61. M. Arif Samad, José A. B. Fortes
    Explanation Capabilities in DEFT : A Design-For-Testability Expert System. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:954-963 [Conf]
  62. Yue Li, Tao Li, Tamer Kahveci, José A. B. Fortes
    Workload Characterization of Bioinformatics Applications. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 2005, pp:15-22 [Conf]
  63. Xin Fu, James Poe, Tao Li, José A. B. Fortes
    Characterizing Microarchitecture Soft Error Vulnerability Phase Behavior. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 2006, pp:147-155 [Conf]
  64. Fernando J. Nuñez, José A. B. Fortes
    Performance of Connectionist Learning Algorithms on 2-D SIMD Processor Arrays. [Citation Graph (0, 0)][DBLP]
    NIPS, 1989, pp:810-817 [Conf]
  65. José A. B. Fortes
    In-VIGO: Making the Grid Virtually Yours. [Citation Graph (0, 0)][DBLP]
    NPC, 2004, pp:3- [Conf]
  66. José Miguel, Agustin Arruabarrena, Ramón Beivide, José A. B. Fortes
    An Empirical Evaluation of Techniques for Parallel Discrete-Event Simulation of Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    PDP, 1996, pp:219-226 [Conf]
  67. Thomas J. Downar, Rudolf Eigenmann, José A. B. Fortes
    Issues and Approaches in Parallel Multi-Component and Multi-Physics Simulations. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:916-922 [Conf]
  68. Meenakshi A. Kandaswamy, Valerie E. Taylor, Rudolf Eigenmann, José A. B. Fortes
    Implicit Finite Element Applications: A Case for Matching the Number of Processors to the Dynamics of the Program Execution. [Citation Graph (0, 0)][DBLP]
    PPSC, 1997, pp:- [Conf]
  69. Sumalatha Adabala, Nirav H. Kapadia, José A. B. Fortes
    Performance and Interoperability Issues in Incorporating Cluster Management Systems Within a Wide-Area Network-Computing Environment. [Citation Graph (0, 0)][DBLP]
    SC, 2000, pp:- [Conf]
  70. Ivan Krsul, Arijit Ganguly, Jian Zhang, José A. B. Fortes, Renato J. O. Figueiredo
    VMPlants: Providing and Managing Virtual Machine Execution Environments for Grid Computing. [Citation Graph (0, 0)][DBLP]
    SC, 2004, pp:7- [Conf]
  71. Insung Park, Nirav H. Kapadia, Renato J. O. Figueiredo, Rudolf Eigenmann, José A. B. Fortes
    Towards an Integrated, Web-executable Parallel Programming Tool Environment. [Citation Graph (0, 0)][DBLP]
    SC, 2000, pp:- [Conf]
  72. Rajesh Subramanyan, José Miguel-Alonso, José A. B. Fortes
    A Scalable SNMP-Based Distributed Monitoring System For Heterogeneous Network Computing. [Citation Graph (0, 0)][DBLP]
    SC, 2000, pp:- [Conf]
  73. Nirav H. Kapadia, Carla E. Brodley, José A. B. Fortes, Mark S. Lundstrom
    Resource-Usage Prediction for Demand-Based Network-Computing. [Citation Graph (0, 0)][DBLP]
    Symposium on Reliable Distributed Systems, 1998, pp:372-377 [Conf]
  74. Renato J. O. Figueiredo, José A. B. Fortes, Zina Ben-Miled
    Spatial Data Locality with Respect to Degree of Parallelism in Processor-and-Memory Hierarchies. [Citation Graph (0, 0)][DBLP]
    VECPAR, 1998, pp:396-410 [Conf]
  75. Renato J. O. Figueiredo, Jeffrey P. Bradford, José A. B. Fortes
    Improving the Performance of Heterogeneous DSMs via Multithreading. [Citation Graph (0, 0)][DBLP]
    VECPAR, 2000, pp:168-180 [Conf]
  76. José A. B. Fortes, Benjamin W. Wah, Weijia Shang, Kumar N. Ganapathy
    Algorithm-Specific Parallel Processing with Linear Processor Arrays. [Citation Graph (0, 0)][DBLP]
    Advances in Computers, 1994, v:38, n:, pp:197-245 [Journal]
  77. Hyuk-Jae Lee, José A. B. Fortes
    Communication-Minimal Partitioning and Data Alignment for Affine Nested Loops. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1997, v:40, n:6, pp:302-310 [Journal]
  78. Renato J. O. Figueiredo, Nirav H. Kapadia, José A. B. Fortes
    Seamless Access to Decentralized Storage Services in Computational Grids via a Virtual File System. [Citation Graph (0, 0)][DBLP]
    Cluster Computing, 2004, v:7, n:2, pp:113-122 [Journal]
  79. Nirav H. Kapadia, José A. B. Fortes
    PUNCH: An architecture for Web-enabled wide-area network-computing. [Citation Graph (0, 0)][DBLP]
    Cluster Computing, 1999, v:2, n:2, pp:153-164 [Journal]
  80. Mengly Chean, José A. B. Fortes
    A Taxonomy of Reconfiguration Techniques for Fault-Tolerant Processor Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1990, v:23, n:1, pp:55-69 [Journal]
  81. Renato J. O. Figueiredo, Peter A. Dinda, José A. B. Fortes
    Guest Editors' Introduction: Resource Virtualization Renaissance. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2005, v:38, n:5, pp:28-31 [Journal]
  82. Jie Han, Jianbo Gao, Yan Qi 0003, Pieter Jonker, José A. B. Fortes
    Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:328-339 [Journal]
  83. Sumalatha Adabala, Vineet Chadha, Puneet Chawla, Renato J. O. Figueiredo, José A. B. Fortes, Ivan Krsul, Andréa M. Matsunaga, Maurício O. Tsugawa, Jian Zhang, Ming Zhao, Liping Zhu, Xiaomin Zhu
    From virtualized resources to virtual computing grids: the In-VIGO system. [Citation Graph (0, 0)][DBLP]
    Future Generation Comp. Syst., 2005, v:21, n:6, pp:896-909 [Journal]
  84. Jeffrey P. Bradford, José A. B. Fortes
    Characterization and Parallelization of Decision-Tree Induction. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2001, v:61, n:3, pp:322-349 [Journal]
  85. Ali Raza Butt, Sumalatha Adabala, Nirav H. Kapadia, Renato J. O. Figueiredo, José A. B. Fortes
    Grid-computing portals and security issues. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2003, v:63, n:10, pp:1006-1014 [Journal]
  86. William W. Carlson, José A. B. Fortes
    On the Performance of Combined Data Flow and Control Flow Systems: Experiments Using Two Iterative Algorithms. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1988, v:5, n:4, pp:359-382 [Journal]
  87. Nirav H. Kapadia, Renato J. O. Figueiredo, José A. B. Fortes
    PUNCH: Web Portal for Running Tools. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2000, v:20, n:3, pp:38-47 [Journal]
  88. Hyuk-Jae Lee, José A. B. Fortes
    Modular Mappings and Data Distribution Independent Computations. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1997, v:7, n:2, pp:169-180 [Journal]
  89. Hasan Cam, José A. B. Fortes
    A Fast VLSI-Efficient Self-Routing Permutation Network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:3, pp:448-453 [Journal]
  90. Hasan Cam, José A. B. Fortes
    Frames: A Simple Characterization of Permutations Realized by Frequently Used Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:5, pp:695-697 [Journal]
  91. Mengly Chean, José A. B. Fortes
    The Full-Use-of-Suitable-Spares (FUSS) Approach to Hardware Reconfiguration for Fault-Tolerant Processor Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:4, pp:564-571 [Journal]
  92. José A. B. Fortes, C. S. Raghavendra
    Gracefully Degradable Processor Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:11, pp:1033-1044 [Journal]
  93. Noé Lopez-Benitez, José A. B. Fortes
    Detailed Modeling and Reliability Analysis of Fault-Tolerant Processor Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:9, pp:1193-1200 [Journal]
  94. Dan I. Moldovan, José A. B. Fortes
    Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:1, pp:1-12 [Journal]
  95. Matthew T. O'Keefe, José A. B. Fortes, Benjamin W. Wah
    On the Relationship Between Two Systolic Array Design Mehodologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:12, pp:1589-1593 [Journal]
  96. Darwen Rau, José A. B. Fortes, Howard Jay Siegel
    Destination Tag Routing Techniques Based on a State Model for the IADM Network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:3, pp:274-285 [Journal]
  97. Weijia Shang, José A. B. Fortes
    Time Optimal Linear Schedules for Algorithms with Uniform Dependencies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:6, pp:723-742 [Journal]
  98. Weijia Shang, José A. B. Fortes
    Independent Partitioning of Algorithms with Uniform Dependencies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:2, pp:190-206 [Journal]
  99. Nirav H. Kapadia, José A. B. Fortes, Mark S. Lundstrom
    The Purdue University network-computing hubs: running unmodified simulation tools via the WWW. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Model. Comput. Simul., 2000, v:10, n:1, pp:39-57 [Journal]
  100. Hasan Cam, José A. B. Fortes
    Work-Efficient Routing Algorithms for Rearrangeable Symmetrical Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1999, v:10, n:7, pp:733-741 [Journal]
  101. Hyuk-Jae Lee, José A. B. Fortes
    Generation of Injective and Reversible Modular Mappings. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2003, v:14, n:1, pp:1-12 [Journal]
  102. Weijia Shang, José A. B. Fortes
    On Time Mapping of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1992, v:3, n:3, pp:350-363 [Journal]
  103. Weijia Shang, Matthew T. O'Keefe, José A. B. Fortes
    On Loop Transformations for Generalized Cycle Shrinking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:2, pp:193-204 [Journal]
  104. Jing Xu, Ming Zhao, José A. B. Fortes, Robert Carpenter, Mazin S. Yousif
    On the Use of Fuzzy Modeling in Virtualized Data Center Management. [Citation Graph (0, 0)][DBLP]
    ICAC, 2007, pp:25- [Conf]
  105. Jack DiGiovanna, Loris Marchal, Prapaporn Rattanatamrong, Ming Zhao, Shalom Darmanjian, Babak Mahmoudi, Justin C. Sanchez, José C. Príncipe, Linda Hermer-Vazquez, Renato J. O. Figueiredo, José A. B. Fortes
    Towards Real-Time Distributed Signal Modeling for Brain-Machine Interfaces. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science (1), 2007, pp:964-971 [Conf]

  106. On the Use of Machine Learning to Predict the Time and Resources Consumed by Applications. [Citation Graph (, )][DBLP]


  107. Sky Computing: When Multiple Clouds Become One. [Citation Graph (, )][DBLP]


  108. Combined circuit and microarchitecture techniques for effective soft error robustness in SMT processors. [Citation Graph (, )][DBLP]


  109. Development of Symbiotic Brain-Machine Interfaces Using a Neurophysiology Cyberworkstation. [Citation Graph (, )][DBLP]


  110. Soft error vulnerability aware process variation mitigation. [Citation Graph (, )][DBLP]


  111. In-VIGO virtual networks and virtual application services: automated grid-enabling and deployment of applications. [Citation Graph (, )][DBLP]


  112. Real-time scheduling of mixture-of-experts systems with limited resources. [Citation Graph (, )][DBLP]


  113. Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures. [Citation Graph (, )][DBLP]


  114. An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures. [Citation Graph (, )][DBLP]


  115. NBTI tolerant microarchitecture design in the presence of process variation. [Citation Graph (, )][DBLP]


  116. ORBIT: Effective Issue Queue Soft-Error Vulnerability Mitigation on Simultaneous Multithreaded Architectures Using Operand Readiness-Based Instruction Dispatch. [Citation Graph (, )][DBLP]


  117. Cooperative Autonomic Management in Dynamic Distributed Systems. [Citation Graph (, )][DBLP]


  118. Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education. [Citation Graph (, )][DBLP]


  119. Autonomic resource management in virtualized data centers using fuzzy logic-based approaches. [Citation Graph (, )][DBLP]


  120. Science gateways made easy: the In-VIGO approach. [Citation Graph (, )][DBLP]


  121. Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education [Citation Graph (, )][DBLP]


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