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Thomas P. Kelliher:
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Publications of Author
- Shrirang M. Yardi, Benjamin Bishop, Thomas P. Kelliher
HELLAS: a specialized architecture for interactive deformable object modeling. [Citation Graph (0, 0)][DBLP] ACM Southeast Regional Conference, 2006, pp:56-61 [Conf]
- Kevin P. Acken, Eric Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin
The MGAP Family of Processor Arrays. [Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1997, pp:105-0 [Conf]
- Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin
SPARTA: Simulation of Physics on a Real-Time Architecture. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2000, pp:177-182 [Conf]
- Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin
The Design of a Register Renaming Unit. [Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1999, pp:34-37 [Conf]
- Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin
Hardware/Software Co-design for Real-Time Physical Modeling. [Citation Graph (0, 0)][DBLP] IEEE International Conference on Multimedia and Expo (III), 2000, pp:1363-1366 [Conf]
- Shrirang M. Yardi, Benjamin Bishop, Thomas P. Kelliher
An Analysis of Iterative Deformable Solid Object Modeling. [Citation Graph (0, 0)][DBLP] MSV, 2005, pp:95-99 [Conf]
- Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin, TingTing Hwang
ELM-A Fast Addition Algorithm Discovered by a Program. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1992, v:41, n:9, pp:1181-1184 [Journal]
- Benjamin Bishop, Thomas P. Kelliher
Specialized hardware for deformable object modeling. [Citation Graph (0, 0)][DBLP] IEEE Trans. Circuits Syst. Video Techn., 2003, v:13, n:11, pp:1074-1079 [Journal]
- Robert Michael Owens, Thomas P. Kelliher, Mary Jane Irwin, Mohan Vishwanath, Raminder Singh Bajwa, W.-L. Yang
The design and implementation of the Arithmetic Cube II, a VLSI signal processing system. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:491-502 [Journal]
- Gayles Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin
The design of the MGAP-2: a micro-grained massively parallel array. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:709-716 [Journal]
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