The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Thomas P. Kelliher: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shrirang M. Yardi, Benjamin Bishop, Thomas P. Kelliher
    HELLAS: a specialized architecture for interactive deformable object modeling. [Citation Graph (0, 0)][DBLP]
    ACM Southeast Regional Conference, 2006, pp:56-61 [Conf]
  2. Kevin P. Acken, Eric Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin
    The MGAP Family of Processor Arrays. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:105-0 [Conf]
  3. Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin
    SPARTA: Simulation of Physics on a Real-Time Architecture. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:177-182 [Conf]
  4. Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin
    The Design of a Register Renaming Unit. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:34-37 [Conf]
  5. Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin
    Hardware/Software Co-design for Real-Time Physical Modeling. [Citation Graph (0, 0)][DBLP]
    IEEE International Conference on Multimedia and Expo (III), 2000, pp:1363-1366 [Conf]
  6. Shrirang M. Yardi, Benjamin Bishop, Thomas P. Kelliher
    An Analysis of Iterative Deformable Solid Object Modeling. [Citation Graph (0, 0)][DBLP]
    MSV, 2005, pp:95-99 [Conf]
  7. Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin, TingTing Hwang
    ELM-A Fast Addition Algorithm Discovered by a Program. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:9, pp:1181-1184 [Journal]
  8. Benjamin Bishop, Thomas P. Kelliher
    Specialized hardware for deformable object modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2003, v:13, n:11, pp:1074-1079 [Journal]
  9. Robert Michael Owens, Thomas P. Kelliher, Mary Jane Irwin, Mohan Vishwanath, Raminder Singh Bajwa, W.-L. Yang
    The design and implementation of the Arithmetic Cube II, a VLSI signal processing system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:491-502 [Journal]
  10. Gayles Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin
    The design of the MGAP-2: a micro-grained massively parallel array. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:709-716 [Journal]

Search in 0.002secs, Finished in 0.002secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002