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Fredrik Dahlgren: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Fredrik Dahlgren
    A program-driven simulation model of an MIMD multiprocessor. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 1991, pp:40-49 [Conf]
  2. Fredrik Dahlgren
    Partial Continuous Functions and Admissible Domain Representations. [Citation Graph (0, 0)][DBLP]
    CiE, 2006, pp:94-104 [Conf]
  3. Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec
    Topic 08+13: Instruction-Level Parallelism and Computer Architecture. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2001, pp:385- [Conf]
  4. Mårten Björkman, Fredrik Dahlgren, Per Stenström
    Using hints to reduce the read miss penalty for flat COMA protocols. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1995, pp:242-251 [Conf]
  5. Frederic T. Chong, Rajeev Barua, Fredrik Dahlgren, John Kubiatowicz, Anant Agarwal
    The Sensitivity of Communication Mechanisms to Bandwidth and Latency. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:37-46 [Conf]
  6. Fredrik Dahlgren, Per Stenström
    Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:68-77 [Conf]
  7. Fredrik Dahlgren, Anders Landin
    Reducing the Replacement Overhead in Bus-Based COMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:14-23 [Conf]
  8. Magnus Karlsson, Fredrik Dahlgren, Per Stenström
    A Prefetching Technique for Irregular Accesses to Linked Data Structures. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:206-217 [Conf]
  9. Anders Landin, Fredrik Dahlgren
    Bus-Based COMA - Reducing Traffic in Shared-Bus Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:95-105 [Conf]
  10. Fredrik Dahlgren
    Future Mobile Phones--Complex Design Challenges from an Embedded Systems Perspective. [Citation Graph (0, 0)][DBLP]
    ICECCS, 2001, pp:92-0 [Conf]
  11. Fredrik Dahlgren, Michel Dubois, Per Stenström
    Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:56-63 [Conf]
  12. Fredrik Dahlgren, Per Stenström
    Reducing the Write Traffic for a Hybrid Cache Protocol. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1994, pp:166-173 [Conf]
  13. Jim Nilsson, Fredrik Dahlgren
    Improving Performance of Load-Store Sequences for Transaction Processing Workloads on Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1999, pp:246-0 [Conf]
  14. Per Stenström, Fredrik Dahlgren, Lars Lundberg
    A Lockup-Free Multiprocessor Cache Design. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:246-250 [Conf]
  15. Ashley Saulsbury, Su-Jaen Huang, Fredrik Dahlgren
    Efficient management of memory hierarchies in embedded DRAM systems. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:464-473 [Conf]
  16. Martin Kämpe, Fredrik Dahlgren
    Exploration of the Spatial Locality on Emerging Applications and the Consequences for Cache Performance. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:163-170 [Conf]
  17. Jim Nilsson, Fredrik Dahlgren
    Reducing Ownership Overhead for Load-Store Sequences in Cache-Coherent Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:684-692 [Conf]
  18. Fredrik Dahlgren
    Boosting the Performance of Hybrid Snooping Cache Protocols. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:60-69 [Conf]
  19. Fredrik Dahlgren, Michel Dubois, Per Stenström
    Combined Performance Gains of Simple Cache Protocol Extensions. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:187-197 [Conf]
  20. Ashley Saulsbury, Fredrik Dahlgren, Per Stenström
    Recency-based TLB preloading. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:117-127 [Conf]
  21. Magnus Ekman, Per Stenström, Fredrik Dahlgren
    TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:243-246 [Conf]
  22. Fredrik Dahlgren, Per Stenström
    On Reconfigurable On-Chip Data Caches. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:189-198 [Conf]
  23. Fredrik Dahlgren, Per Stenström, Mårten Björkman
    Reducing the Read-Miss Penalty for Flat COMA Protocols. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1997, v:40, n:4, pp:208-219 [Journal]
  24. Fredrik Dahlgren, Josep Torrellas
    Cache-Only Memory Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1999, v:32, n:6, pp:72-79 [Journal]
  25. Per Stenström, Mats Brorsson, Fredrik Dahlgren, Håkan Grahn, Michel Dubois
    Boosting the Performance of Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:7, pp:63-70 [Journal]
  26. Per Stenström, Fredrik Dahlgren
    Applications for Shared Memory Multiprocessors (Guest Editors' Introduction). [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1996, v:29, n:12, pp:29-31 [Journal]
  27. Fredrik Dahlgren
    Techniques for Improving Performance of Hybrid Snooping Cache Protocols. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1999, v:59, n:3, pp:329-359 [Journal]
  28. Fredrik Dahlgren, Per Stenström
    Using Write Caches to Improve Performance of Cache Coherence Protocols in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1995, v:26, n:2, pp:193-210 [Journal]
  29. Jonas Skeppstedt, Fredrik Dahlgren, Per Stenström
    Evaluation of Compiler-Controlled Updating to Reduce Coherence-Miss Penalties in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1999, v:56, n:2, pp:122-143 [Journal]
  30. Fredrik Dahlgren
    Computability and continuity in metric partial algebras equipped with computability structures. [Citation Graph (0, 0)][DBLP]
    Math. Log. Q., 2004, v:50, n:4-5, pp:486-500 [Journal]
  31. Fredrik Dahlgren, Michel Dubois, Per Stenström
    Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:10, pp:1041-1055 [Journal]
  32. Fredrik Dahlgren, Michel Dubois, Per Stenström
    Sequential Hardware Prefetching in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1995, v:6, n:7, pp:733-746 [Journal]
  33. Fredrik Dahlgren, Per Stenström
    Evaluation of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1996, v:7, n:4, pp:385-398 [Journal]

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