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Dirk Stroobandt :
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Lieven Eeckhout , Dirk Stroobandt , Koenraad De Bosschere Efficient Microprocessor Design Space Exploration through Statistical Simulatio. [Citation Graph (0, 0)][DBLP ] Annual Simulation Symposium, 2003, pp:233-240 [Conf ] Chung-Kuan Cheng , Andrew B. Kahng , Bao Liu , Dirk Stroobandt Toward better wireload models in the presence of obstacles. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2001, pp:527-532 [Conf ] Dirk Stroobandt , Jan Van Campenhout Hierarchical Test Generation with Built-In Fault Diagnosis. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 1996, pp:22-28 [Conf ] Andrew E. Caldwell , Yu Cao , Andrew B. Kahng , Farinaz Koushanfar , Hua Lu , Igor L. Markov , Michael Oliver , Dirk Stroobandt , Dennis Sylvester GTX: the MARCO GSRC technology extrapolation system. [Citation Graph (0, 0)][DBLP ] DAC, 2000, pp:693-698 [Conf ] Hendrik Eeckhaut , Harald Devos , Benjamin Schrauwen , Mark Christiaens , Dirk Stroobandt A Hardware-Friendly Wavelet Entropy Codec for Scalable Video. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:14-19 [Conf ] David Verstraeten , Benjamin Schrauwen , Dirk Stroobandt Isolated word recognition using a Liquid State Machine. [Citation Graph (0, 0)][DBLP ] ESANN, 2005, pp:435-440 [Conf ] Philippe Faes , Mark Christiaens , Dries Buytaert , Dirk Stroobandt FPGA-Aware Garbage Collection in Java. [Citation Graph (0, 0)][DBLP ] FPL, 2005, pp:675-680 [Conf ] Herwig Van Marck , Jo Depreitere , Dirk Stroobandt , Jan Van Campenhout A Quantitative Study of the Benefits of Area-I/O in FPGAs. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1998, pp:392-399 [Conf ] Dirk Stroobandt On an Efficient Method for Estimating the Interconnection Complexity of Designs and on the Existence of Region III in Rent's Rule. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1999, pp:330-331 [Conf ] Dirk Stroobandt , Fadi J. Kurdahi On the Characterization of Multi-Point Nets in Electronic Designs. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1998, pp:344-0 [Conf ] Dirk Stroobandt , Herwig Van Marck , Jan Van Campenhout An Accurate Interconnection Length Estimation for Computer Logic. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1996, pp:50-55 [Conf ] Michiel De Wilde , Dirk Stroobandt , Jan Van Campenhout AQUASUN : adaptive window query processing in CAD applications for physical design and verification. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2002, pp:153-159 [Conf ] Michiel D'Haene , Benjamin Schrauwen , Dirk Stroobandt Accelerating Event Based Simulation for Multi-synapse Spiking Neural Networks. [Citation Graph (0, 0)][DBLP ] ICANN (1), 2006, pp:760-769 [Conf ] Yu Cao , Chenming Hu , Xuejue Huang , Andrew B. Kahng , Sudhakar Muddu , Dirk Stroobandt , Dennis Sylvester Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. [Citation Graph (0, 0)][DBLP ] ICCAD, 2000, pp:56-61 [Conf ] Andrew B. Kahng , Stefanus Mantik , Dirk Stroobandt Requirements for models of achievable routing. [Citation Graph (0, 0)][DBLP ] ISPD, 2000, pp:4-11 [Conf ] Dirk Stroobandt , Peter Verplaetse , Jan Van Campenhout Towards synthetic benchmark circuits for evaluating timing-driven CAD tools. [Citation Graph (0, 0)][DBLP ] ISPD, 1999, pp:60-66 [Conf ] Ian O'Connor , Matthieu Briere , Emmanuel Drouard , Art Kazmierczak , Faress Tissafi-Drissi , David Navarro , Fabien Mieyeville , Joni Dambre , Dirk Stroobandt , J.-M. Fedeli , Zbigniew Lisik , Frédéric Gaffiot Towards reconfigurable optical networks on chip. [Citation Graph (0, 0)][DBLP ] ReCoSoC, 2005, pp:121-128 [Conf ] Dirk Stroobandt , Hendrik Eeckhaut , Harald Devos , Mark Christiaens , Fabio Verdicchio , Peter Schelkens Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements. [Citation Graph (0, 0)][DBLP ] SAMOS, 2004, pp:203-212 [Conf ] Dirk Stroobandt A priori system-level interconnect prediction: Rent's rule and wire length distribution models. [Citation Graph (0, 0)][DBLP ] SLIP, 2001, pp:3-21 [Conf ] Dirk Stroobandt , Herwig Van Marck Efficient representation of interconnection length distributions using generating polynomials. [Citation Graph (0, 0)][DBLP ] SLIP, 2000, pp:99-105 [Conf ] Joni Dambre , Dirk Stroobandt , Jan Van Campenhout Fast estimation of the partitioning rent characteristic using a recursive partitioning model. [Citation Graph (0, 0)][DBLP ] SLIP, 2003, pp:45-52 [Conf ] Joni Dambre , Peter Verplaetse , Dirk Stroobandt , Jan Van Campenhout On rent's rule for rectangular regions. [Citation Graph (0, 0)][DBLP ] SLIP, 2001, pp:49-56 [Conf ] Joni Dambre , Peter Verplaetse , Dirk Stroobandt , Jan Van Campenhout Getting more out of Donath's hierarchical model for interconnect prediction. [Citation Graph (0, 0)][DBLP ] SLIP, 2002, pp:9-16 [Conf ] Peter Verplaetse , Joni Dambre , Dirk Stroobandt , Jan Van Campenhout On partitioning vs. placement rent properties. [Citation Graph (0, 0)][DBLP ] SLIP, 2001, pp:33-40 [Conf ] Wim Heirman , Joni Dambre , Christof Debaes , Hugo Thienpont , Dirk Stroobandt , Jan Van Campenhout Prediction model for evaluation of reconfigurable interconnects in distributed shared-memory systems. [Citation Graph (0, 0)][DBLP ] SLIP, 2005, pp:51-58 [Conf ] Andrew B. Kahng , Dirk Stroobandt Wiring layer assignments with consistent stage delays. [Citation Graph (0, 0)][DBLP ] SLIP, 2000, pp:115-122 [Conf ] Joni Dambre , Dirk Stroobandt , Jan Van Campenhout A probabilistic approach to clock cycle prediction. [Citation Graph (0, 0)][DBLP ] Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:9-15 [Conf ] Dirk Stroobandt , Jo Depreitere , Jan Van Campenhout Generating new benchmark designs using a multi-terminal net model. [Citation Graph (0, 0)][DBLP ] Integration, 1999, v:27, n:2, pp:113-129 [Journal ] David Verstraeten , Benjamin Schrauwen , Dirk Stroobandt , Jan Van Campenhout Isolated word recognition with the Liquid State Machine : a case study. [Citation Graph (0, 0)][DBLP ] Inf. Process. Lett., 2005, v:95, n:6, pp:521-528 [Journal ] Andrew B. Kahng , Stefanus Mantik , Dirk Stroobandt Toward accurate models of achievable routing. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:648-659 [Journal ] Dirk Stroobandt , Peter Verplaetse , Jan M. Van Campenhout Generating synthetic benchmark circuits for evaluating CAD tools. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1011-1022 [Journal ] Joni Dambre , Dirk Stroobandt , Jan Van Campenhout Toward the accurate prediction of placement wire length distributions in VLSI circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:339-348 [Journal ] Eric A. Antonelo , Benjamin Schrauwen , Xavier Dutoit , Dirk Stroobandt , Marnix Nuttin Event Detection and Localization in Mobile Robot Navigation Using Reservoir Computing. [Citation Graph (0, 0)][DBLP ] ICANN (2), 2007, pp:660-669 [Conf ] Philippe Faes , Mark Christiaens , Dirk Stroobandt Mobility of Data in Distributed Hybrid Computing Systems. [Citation Graph (0, 0)][DBLP ] IPDPS, 2007, pp:1-7 [Conf ] Hendrik Eeckhaut , Harald Devos , Dirk Stroobandt The Energy Scalability of Wavelet-Based, Scalable Video Decoding. [Citation Graph (0, 0)][DBLP ] PATMOS, 2007, pp:363-372 [Conf ] Hendrik Eeckhaut , Harald Devos , Philippe Faes , Mark Christiaens , Dirk Stroobandt FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder. [Citation Graph (0, 0)][DBLP ] SAMOS, 2007, pp:169-178 [Conf ] Igor L. Markov , Louis Scheffer , Dirk Stroobandt Special issue on System-Level Interconnect Prediction. [Citation Graph (0, 0)][DBLP ] Integration, 2007, v:40, n:4, pp:381- [Journal ] Wim Heirman , Joni Dambre , I. Artundo , Christof Debaes , Hugo Thienpont , Dirk Stroobandt , Jan M. Van Campenhout Predicting reconfigurable interconnect performance in distributed shared-memory systems. [Citation Graph (0, 0)][DBLP ] Integration, 2007, v:40, n:4, pp:382-393 [Journal ] David Verstraeten , Benjamin Schrauwen , Michiel D'Haene , Dirk Stroobandt An experimental unification of reservoir computing methods. [Citation Graph (0, 0)][DBLP ] Neural Networks, 2007, v:20, n:3, pp:391-403 [Journal ] Ian O'Connor , Faress Tissafi-Drissi , Frédéric Gaffiot , Joni Dambre , Michiel De Wilde , Jan Van Campenhout , D. Van Thourhout , Dirk Stroobandt Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:927-940 [Journal ] P. Christie , Dirk Stroobandt The interpretation and application of Rent's rule. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:639-648 [Journal ] Peter Verplaetse , Dirk Stroobandt , Jan M. Van Campenhout A stochastic model for the interconnection topology of digital circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:938-942 [Journal ] Dirk Stroobandt Guest editorial - system-level interconnect prediction. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:175-176 [Journal ] Chung-Kuan Cheng , Andrew B. Kahng , Bao Liu , Dirk Stroobandt Toward better wireload models in the presence of obstacles. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:177-189 [Journal ] J. Dambre , Peter Verplaetse , Dirk Stroobandt , Jan Van Campenhout A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:24-34 [Journal ] Yu Cao , Chenming Hu , Xuejue Huang , Andrew B. Kahng , Igor L. Markov , Michael Oliver , Dirk Stroobandt , Dennis Sylvester Improved a priori interconnect predictions and technology extrapolation in the GTX system. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:3-14 [Journal ] Dirk Stroobandt A priori wire length distribution models with multiterminal nets. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:35-43 [Journal ] Strategies for dynamic memory allocation in hybrid architectures. [Citation Graph (, )][DBLP ] Energy Scalability and the RESUME Scalable Video Codec. [Citation Graph (, )][DBLP ] Automatically mapping applications to a self-reconfiguring platform. [Citation Graph (, )][DBLP ] Optimizing the FPGA Memory Design for a Sobel Edge Detector. [Citation Graph (, )][DBLP ] Adapting reservoir states to get Gaussian distributions. [Citation Graph (, )][DBLP ] Pruning and Regularisation in Reservoir Computing: a First Insight. [Citation Graph (, )][DBLP ] Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only). [Citation Graph (, )][DBLP ] A Method for Fast Hardware Specialization at run-time. [Citation Graph (, )][DBLP ] Improving External Memory Access for Avalon Systems on Programmable Chips.. [Citation Graph (, )][DBLP ] Automatic generation of run-time parameterizable configurations. [Citation Graph (, )][DBLP ] Stable Output Feedback in Reservoir Computing Using Ridge Regression. [Citation Graph (, )][DBLP ] Real-Time Epileptic Seizure Detection on Intra-cranial Rat Data Using Reservoir Computing. [Citation Graph (, )][DBLP ] Mobile robot control in the road sign problem using Reservoir Computing networks. [Citation Graph (, )][DBLP ] Reservoir-based techniques for speech recognition. [Citation Graph (, )][DBLP ] Band-pass Reservoir Computing. [Citation Graph (, )][DBLP ] Parallel Computing with FPGAs - Concepts and Applications. [Citation Graph (, )][DBLP ] Imitation Learning of an Intelligent Navigation System for Mobile Robots Using Reservoir Computing. [Citation Graph (, )][DBLP ] Rent's rule and parallel programs: characterizing network traffic behavior. [Citation Graph (, )][DBLP ] Towards a Tighter Integration of Generated and Custom-Made Hardware. [Citation Graph (, )][DBLP ] TROUTE: A Reconfigurability-Aware FPGA Router. [Citation Graph (, )][DBLP ] Scalable hardware accelerator for comparing DNA and protein sequences. [Citation Graph (, )][DBLP ] Java and the Power of Multi-Core Processing. [Citation Graph (, )][DBLP ] Efficient measurement of data flow enabling communication-aware parallelisation. [Citation Graph (, )][DBLP ] Reconfigurability-Aware Structural Mapping for LUT-Based FPGAs. [Citation Graph (, )][DBLP ] Loop Transformations to Reduce the Dynamic FPGA Recon?guration Overhead. [Citation Graph (, )][DBLP ] Search in 0.004secs, Finished in 0.472secs