|
Search the dblp DataBase
Youngmin Hur:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- Youngmin Hur, Stephen A. Szygenda
Special purpose array processor for digital logic simulation. [Citation Graph (0, 0)][DBLP] Annual Simulation Symposium, 1995, pp:297-302 [Conf]
- Youngmin Hur, Stephen A. Szygenda
A Simulation Tool for Design Error Models Utilizing Error Compression and Sampling. [Citation Graph (0, 0)][DBLP] Annual Simulation Symposium, 1996, pp:212-220 [Conf]
- Youngmin Hur, Saghir A. Shaikh, Silvian Goldenberg, D. Kacprzak, Stephen A. Szygenda
Concurrent Fault and Design Error Simulation in Interactive Simulation Automation System. [Citation Graph (0, 0)][DBLP] Annual Simulation Symposium, 1997, pp:168-176 [Conf]
- Youngmin Hur, Stephen A. Szygenda, E. Scott Fehr, Granville E. Ott, Sungho Kang
Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation. [Citation Graph (0, 0)][DBLP] HPCA, 1995, pp:340-347 [Conf]
Search in 0.001secs, Finished in 0.001secs
|