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Saghir A. Shaikh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Youngmin Hur, Saghir A. Shaikh, Silvian Goldenberg, D. Kacprzak, Stephen A. Szygenda
    Concurrent Fault and Design Error Simulation in Interactive Simulation Automation System. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 1997, pp:168-176 [Conf]
  2. Saghir A. Shaikh, Stephen A. Szygenda
    Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 1997, pp:64-0 [Conf]
  3. Salem Abdennadher, Saghir A. Shaikh
    Practices in Testing of Mixed-Signal and RF SoCs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:467- [Conf]
  4. Salem Abdennadher, Saghir A. Shaikh
    Challenges in High Speed Interface Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:468- [Conf]
  5. Brian Grayson, Saghir A. Shaikh, Stephen A. Szygenda
    Statistics on concurrent fault and design error simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:622-627 [Conf]
  6. John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly
    Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:258-267 [Conf]
  7. Saghir A. Shaikh
    IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps Transceiver. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:543-550 [Conf]
  8. Saghir A. Shaikh, Silvian Goldenberg, Stephen A. Szygenda
    CON2FERS: A Concurrent Concurrent Fault and Design Error Simulator. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1996, pp:109-112 [Conf]
  9. Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, Saghir A. Shaikh, M. d'Abreu
    Maximizing Wafer Productivity Through Layout Optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:192-197 [Conf]
  10. Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken
    Manufacturability and Testability Oriented Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:185-191 [Conf]
  11. A. Bommireddy, Jitendra Khare, Saghir A. Shaikh, S.-T. Su
    Test and Debug of Networking SoCs: A Case Study. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:121-126 [Conf]

  12. Practices in Mixed-Signal and RF IC Testing. [Citation Graph (, )][DBLP]


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