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Alain Greiner: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Frédéric Pétrot, Denis Hommais, Alain Greiner
    A Simulation Environment for Core Based Embedded Systems. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 1997, pp:86-91 [Conf]
  2. Rabie Ben Atitallah, Smaïl Niar, Alain Greiner, Samy Meftali, Jean-Luc Dekeyser
    Estimating Energy Consumption for an MPSoC Architectural Exploration. [Citation Graph (0, 0)][DBLP]
    ARCS, 2006, pp:298-310 [Conf]
  3. Adrijean Andriahantenaina, Hervé Charlery, Alain Greiner, Laurent Mortiez, Cesar Albenes Zeferino
    SPIN: A Scalable, Packet Switched, On-Chip Micro-Network. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20070-20073 [Conf]
  4. Adrijean Andriahantenaina, Alain Greiner
    Micro-Network for SoC: Implementation of a 32-Port SPIN network. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11128-11129 [Conf]
  5. Mounir Benabdenbi, Alain Greiner, François Pêcheux, Emmanuel Viaud, Matthieu Tuna
    STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:712-713 [Conf]
  6. Mohamed Dessouky, Andreas Kaiser, Marie-Minerve Louërat, Alain Greiner
    Analog design for reuse - case study: very low-voltage sigma-delta modulator. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:353-360 [Conf]
  7. Pierre Guerrier, Alain Greiner
    A Generic Architecture for On-Chip Packet-Switched Interconnections. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:250-256 [Conf]
  8. Emmanuel Viaud, François Pêcheux, Alain Greiner
    An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:94-99 [Conf]
  9. Frédéric Pétrot, Alain Greiner, Pascal Gomez
    On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:53-60 [Conf]
  10. Luc Burgun, N. Dictus, Alain Greiner, E. Pradho, C. Sarwary
    Multilevel Logic Synthesis of Very High Complexity Circuits. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:669- [Conf]
  11. Alain Greiner, L. Lucas, Franck Wajsbürt, Laurent Winckel
    Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:9-13 [Conf]
  12. M. Hirech, O. Florent, Alain Greiner, E. Rejouan
    A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:668- [Conf]
  13. Frédéric Pétrot, Denis Hommais, Alain Greiner
    Cycle precise core based hardware/software system simulation with predictable event propagation. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1997, pp:182-187 [Conf]
  14. Denis Archambaud, Pascal Faudemay, Alain Greiner
    RAPID-2, An Object-Oriented Associative Memory Applicable to Genome Data Processing. [Citation Graph (0, 0)][DBLP]
    HICSS (5), 1994, pp:150-159 [Conf]
  15. Lotfi Ben Ammar, Alain Greiner
    FITPATH: A Process-Independent Datapath Compiler Providing High Density Layout. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:133-151 [Conf]
  16. Jean Lou Desbarbieux, Olivier Gluck, Amal Zerrouki, Alexandre Fenyo, Alain Greiner, Franck Wajsbürt, Cyril Spasevski, Fabrício Silva, E. Dreyfus
    Protocol and Performance Analysis of the MPC Parallel Computer. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:52- [Conf]
  17. Marcello Duhalde, Alain Greiner, Frédéric Pétrot
    A High Performance Modular Embedded ROM Architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1057-1060 [Conf]
  18. M. Hirech, O. Florent, Alain Greiner, E. Rejouan
    A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:89-92 [Conf]
  19. A. Sheibanyrad, Alain Greiner
    Two Efficient Synchronous Û Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:191-202 [Conf]
  20. Etienne Faure, Alain Greiner, Daniela Genius
    A generic hardware/software communication mechanism for Multi-Processor System on Chip, Targeting Telecommunication Applications. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:237-242 [Conf]
  21. Alain Greiner, Frédéric Pétrot, M. Carrier, Mounir Benabdenbi, R. Chotin-Avot, Raphaël Labayrade
    MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:24-30 [Conf]
  22. Matthieu Tuna, Mounir Benabdenbi, Alain Greiner
    At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:447-454 [Conf]
  23. A. Sheibanyrad, Ivan Miro Panades, Alain Greiner
    Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1090-1095 [Conf]
  24. Ivan Miro Panades, Alain Greiner
    Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:83-94 [Conf]
  25. Hervé Charlery, Adrijean Andriahantenaina, Alain Greiner
    Physical design of the VCI wrappers for the on-chip packet-switched network named SPIN. [Citation Graph (0, 0)][DBLP]
    Computers & Electrical Engineering, 2007, v:33, n:4, pp:299-309 [Journal]

  26. Hybrid-Timing FIFOs to Use on Networks-on-Chip in GALS Architectures. [Citation Graph (, )][DBLP]

  27. A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip. [Citation Graph (, )][DBLP]

  28. Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations. [Citation Graph (, )][DBLP]

  29. Using C to write portable CMOS VLSI module generators. [Citation Graph (, )][DBLP]

  30. Multilevel logic optimization of very high complexity circuits. [Citation Graph (, )][DBLP]

  31. A Generic Instruction Set Simulator API for Timed and Untimed Simulation and Debug of MP2-SoCs. [Citation Graph (, )][DBLP]

  32. Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture. [Citation Graph (, )][DBLP]

  33. A language to desing generators of analog functions (poster). [Citation Graph (, )][DBLP]

  34. Multisynchronous and Fully Asynchronous NoCs for GALS Architectures. [Citation Graph (, )][DBLP]

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