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Naraig Manjikian: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Naraig Manjikian, Wayne M. Loucks
    Using split event sets to form and schedule event combinations in discrete event simulation. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 1992, pp:184-191 [Conf]
  2. Naraig Manjikian
    A Vector Multiprocessor for Real-Time Multi-User Detection in Spread-Spectrum Communication. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:185-194 [Conf]
  3. Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic
    Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:427-432 [Conf]
  4. A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
    Design and Implementation of the NUMAchine Multiprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:66-69 [Conf]
  5. R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
    The NUMAchine Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICPP, 2000, pp:487-496 [Conf]
  6. Naraig Manjikian
    Combining Loop Fusion with Prefetching on Shared-memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1997, pp:78-0 [Conf]
  7. Naraig Manjikian, Tarek S. Abdelrahman
    Fusion of Loops for Parallelism and Locality. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1995, pp:19-28 [Conf]
  8. Naraig Manjikian, Tarek S. Abdelrahman
    Scheduling of Wavefront Parallelism on Scalable Shared-memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, Vol. 3, 1996, pp:122-131 [Conf]
  9. Naraig Manjikian, Huang Jin, James Reed, Nathan Cordeiro
    Architecture and Implementation of Chip Multiprocessors: Custom Logic Components and Software for Rapid Prototyping. [Citation Graph (0, 0)][DBLP]
    ICPP, 2004, pp:483-492 [Conf]
  10. Tarek S. Abdelrahman, Naraig Manjikian, Gary Liu, Sudarsan Tandri
    Locality Enhancement for Large-Scale Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    LCR, 1998, pp:335-342 [Conf]
  11. Peter M. Ewert, Naraig Manjikian
    Optimizing software performance for IP frame reassembly in an integrated architecture. [Citation Graph (0, 0)][DBLP]
    Workshop on Software and Performance, 2000, pp:29-37 [Conf]
  12. Peter M. Ewert, Naraig Manjikian
    Hardware/software tradeoffs for IP-over-ATM frame reassembly in an integrated architecture. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 2001, v:24, n:9, pp:768-780 [Journal]
  13. Naraig Manjikian
    More enhancements of the simplescalar tool set. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2001, v:29, n:4, pp:5-12 [Journal]
  14. Naraig Manjikian
    Multiprocessor enhancements of the SimpleScalar tool set. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2001, v:29, n:1, pp:8-15 [Journal]
  15. Naraig Manjikian, Tarek S. Abdelrahman
    Exploiting Wavefront Parallelism on Large-Scale Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2001, v:12, n:3, pp:259-271 [Journal]
  16. Naraig Manjikian, Tarek S. Abdelrahman
    Fusion of Loops for Parallelism and Locality. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1997, v:8, n:2, pp:193-209 [Journal]
  17. Naraig Manjikian, Cindy Mark, Mohanarajah Sinnathamby, James Reed, Huang Jin
    Enhancements and Applications of a Versatile Software Tool for High-Level Specification of Single-Chip Systems. [Citation Graph (0, 0)][DBLP]
    CCECE, 2006, pp:793-798 [Conf]

  18. Reliability- and process variation-aware placement for FPGAs. [Citation Graph (, )][DBLP]


  19. Enhanced Architectural Support for Variable-Length Decoding. [Citation Graph (, )][DBLP]


  20. Performance optimization and parallelization of turbo decoding for software-defined radio. [Citation Graph (, )][DBLP]


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