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Manuel J. Bellido: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alejandro Millán, Manuel J. Bellido, Jorge Juan-Chico, David Guerrero, Paulino Ruiz-de-Clavijo, Enrique Ostúa
    Internode: Internal Node Logic Computational Model. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 2003, pp:241-248 [Conf]
  2. Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia, Angel Barriga Barrios, Raúl Jiménez, José L. Huertas
    New CMOS VLSI linear self-timed architectures. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1995, pp:14-23 [Conf]
  3. P. Fortet, Manuel J. Bellido, F. Sivianes, A. V. Medina
    Multimedia System for Instruction and Learning Electronics. [Citation Graph (0, 0)][DBLP]
    CALISCE, 1996, pp:442-444 [Conf]
  4. Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia
    HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:467-471 [Conf]
  5. Manuel J. Bellido, Manuel Valencia, Antonio J. Acosta, Angel Barriga Barrios, José Luis Huertas, Rafael Domínguez-Castro
    A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2019-2022 [Conf]
  6. Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia
    Gate-level simulation of CMOS circuits using the IDDM model. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:483-486 [Conf]
  7. Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia
    Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:316-326 [Conf]
  8. C. Baena, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, C. J. Jiménez, Manuel Valencia
    Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:353-362 [Conf]
  9. David Guerrero, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán
    Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:501-510 [Conf]
  10. Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero
    Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:477-486 [Conf]
  11. Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero, Enrique Ostúa
    Signal Sampling Based Transition Modeling for Digital Gates Characterization. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:829-837 [Conf]
  12. Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia
    Degradation Delay Model Extension to CMOS Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:149-158 [Conf]
  13. Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Alejandro Millán, David Guerrero
    Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:400-408 [Conf]
  14. Manuel Valencia, Manuel J. Bellido, José L. Huertas, Antonio J. Acosta, Santiago Sánchez-Solano
    Modular Asynchronous Arbiter Insensitive to Metastability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:12, pp:1456-1461 [Journal]
  15. David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, J. Viejo
    Static Power Consumption in CMOS Gates Using Independent Bodies. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:404-412 [Conf]

  16. Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. [Citation Graph (, )][DBLP]


  17. Design of a FFT/IFFT module as an IP core suitable for embedded systems. [Citation Graph (, )][DBLP]


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