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David Guerrero: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alejandro Millán, Manuel J. Bellido, Jorge Juan-Chico, David Guerrero, Paulino Ruiz-de-Clavijo, Enrique Ostúa
    Internode: Internal Node Logic Computational Model. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 2003, pp:241-248 [Conf]
  2. Miguel Caballer, David Guerrero, Vicente Hernández, José E. Román, Mariano Alcañiz Raya, José Antonio Gil, J. M. Rubio
    High Performance Virtual Reality Distributed Electronic Commerce: Application for the Furniture and Ceramics Industries. [Citation Graph (0, 0)][DBLP]
    IV, 2002, pp:516-521 [Conf]
  3. David Guerrero, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán
    Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:501-510 [Conf]
  4. Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero
    Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:477-486 [Conf]
  5. Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero, Enrique Ostúa
    Signal Sampling Based Transition Modeling for Digital Gates Characterization. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:829-837 [Conf]
  6. Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Alejandro Millán, David Guerrero
    Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:400-408 [Conf]
  7. Miguel Caballer, David Guerrero, Vicente Hernández, José E. Román
    A Parallel Rendering Algorithm Based on Hierarchical Radiosity. [Citation Graph (0, 0)][DBLP]
    VECPAR, 2002, pp:523-536 [Conf]
  8. David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, J. Viejo
    Static Power Consumption in CMOS Gates Using Independent Bodies. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:404-412 [Conf]
  9. Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero, Enrique Ostúa, J. Viejo
    Accurate Logic-Level Current Estimation for Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:87-94 [Journal]
  10. David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa, J. Viejo
    Improving the Performance of Static CMOS Gates by Using Independent Bodies. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:70-77 [Journal]

  11. Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. [Citation Graph (, )][DBLP]


  12. Design of a FFT/IFFT module as an IP core suitable for embedded systems. [Citation Graph (, )][DBLP]


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