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Publications of Author

1. Alejandro Millán, Manuel J. Bellido, Jorge Juan-Chico, David Guerrero, Paulino Ruiz-de-Clavijo, Enrique Ostúa
   Internode: Internal Node Logic Computational Model. [Citation Graph (0, 0)][DBLP]
   Annual Simulation Symposium, 2003, pp:241-248 [Conf]
   
2. Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia
   HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:467-471 [Conf]
   
3. Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia
   Gate-level simulation of CMOS circuits using the IDDM model. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2001, pp:483-486 [Conf]
   
4. C. Baena, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, C. J. Jiménez, Manuel Valencia
   Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2002, pp:353-362 [Conf]
   
5. Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, J. Viejo
   Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2005, pp:337-347 [Conf]
   
6. David Guerrero, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán
   Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2003, pp:501-510 [Conf]
   
7. Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero
   Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). [Citation Graph (0, 0)][DBLP]
   PATMOS, 2002, pp:477-486 [Conf]
   
8. Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero, Enrique Ostúa
   Signal Sampling Based Transition Modeling for Digital Gates Characterization. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2004, pp:829-837 [Conf]
   
9. Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia
   Degradation Delay Model Extension to CMOS Gates. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2000, pp:149-158 [Conf]
   
10. Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Alejandro Millán, David Guerrero
    Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:400-408 [Conf]
    
11. Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, J. Viejo
    Logic-Level Fast Current Simulation for Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:425-435 [Conf]
    
12. David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, J. Viejo
    Static Power Consumption in CMOS Gates Using Independent Bodies. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:404-412 [Conf]
    
13. Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero, Enrique Ostúa, J. Viejo
    Accurate Logic-Level Current Estimation for Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:87-94 [Journal]
    
14. David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa, J. Viejo
    Improving the Performance of Static CMOS Gates by Using Independent Bodies. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:70-77 [Journal]
    
15. 
    Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. [Citation Graph (, )][DBLP]
    
    
16. 
    Design of a FFT/IFFT module as an IP core suitable for embedded systems. [Citation Graph (, )][DBLP]