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Enrique Ostúa: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Alejandro Millán, Manuel J. Bellido, Jorge Juan-Chico, David Guerrero, Paulino Ruiz-de-Clavijo, Enrique Ostúa
Internode: Internal Node Logic Computational Model. [Citation Graph (0, 0)][DBLP]
Annual Simulation Symposium, 2003, pp:241-248 [Conf] - Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, J. Viejo
Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. [Citation Graph (0, 0)][DBLP]
PATMOS, 2005, pp:337-347 [Conf] - Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero, Enrique Ostúa
Signal Sampling Based Transition Modeling for Digital Gates Characterization. [Citation Graph (0, 0)][DBLP]
PATMOS, 2004, pp:829-837 [Conf] - Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, J. Viejo
Logic-Level Fast Current Simulation for Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP]
PATMOS, 2005, pp:425-435 [Conf] - David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, J. Viejo
Static Power Consumption in CMOS Gates Using Independent Bodies. [Citation Graph (0, 0)][DBLP]
PATMOS, 2007, pp:404-412 [Conf] - Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero, Enrique Ostúa, J. Viejo
Accurate Logic-Level Current Estimation for Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP]
J. Low Power Electronics, 2006, v:2, n:1, pp:87-94 [Journal] - David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa, J. Viejo
Improving the Performance of Static CMOS Gates by Using Independent Bodies. [Citation Graph (0, 0)][DBLP]
J. Low Power Electronics, 2007, v:3, n:1, pp:70-77 [Journal]
Design of a FFT/IFFT module as an IP core suitable for embedded systems. [Citation Graph (, )][DBLP]
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