The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Gerald G. Pechanek: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chris H. L. Moller, Gerald G. Pechanek
    Architectural simulation system for M.f.a.s.t. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 1996, pp:221-0 [Conf]
  2. Gerald G. Pechanek, Stamatis Vassiliadis
    The ManArray( Embedded Processor Architecture. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1348-1355 [Conf]
  3. Stamatis Vassiliadis, E. A. Hakkennes, J. S. S. M. Wong, Gerald G. Pechanek
    The Sum-Absolute-Difference Motion Estimation Accelerato. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:20559-20566 [Conf]
  4. Gerald G. Pechanek, Stamatis Vassiliadis, Nikos Pitsianis
    ManArray Processor Interconnection Network: An Introduction. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:761-765 [Conf]
  5. Gerald G. Pechanek, M. Stojancic, Stamatis Vassiliadis, C. John Glossner
    MFAST: a single chip highly parallel image processing architecture. [Citation Graph (0, 0)][DBLP]
    ICIP, 1995, pp:69-72 [Conf]
  6. Bruce Schulman, Gerald G. Pechanek
    A 90k Gate ``CLB'' for Parallel Distributed Computing. [Citation Graph (0, 0)][DBLP]
    IPDPS Workshops, 2000, pp:831-838 [Conf]
  7. Valentine C. Aikens II, Steven M. Barber, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis
    A Neuro-Architecture with Embedded Learning. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Systems, 1995, pp:103-106 [Conf]
  8. Nikos Pitsianis, Gerald G. Pechanek
    Indirect VLIW memory allocation for the ManArray multiprocessor DSP. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2003, v:31, n:1, pp:69-74 [Journal]

Search in 1.021secs, Finished in 1.021secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002