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## Search the dblp DataBase
Mircea Vladutiu:
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## Publications of Author- Mihai Udrescu, Lucian Prodan, Mircea Vladutiu
**The Bubble Bit Technique as Improvement of HDL-Based Quantum Circuits Simulation.**[Citation Graph (0, 0)][DBLP] Annual Simulation Symposium, 2005, pp:217-224 [Conf] - Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai
**Using Simulated Fault Injection for Fault Tolerance Assessment of Quantum Circuits.**[Citation Graph (0, 0)][DBLP] Annual Simulation Symposium, 2007, pp:213-220 [Conf] - Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
**Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling.**[Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2000, pp:465-470 [Conf] - Mihai Udrescu, Lucian Prodan, Mircea Vladutiu
**Using HDLs for describing quantum circuits: a framework for efficient quantum algorithm simulation.**[Citation Graph (0, 0)][DBLP] Conf. Computing Frontiers, 2004, pp:96-110 [Conf] - Lucian Prodan, Mihai Udrescu, Mircea Vladutiu
**Reliability assessment in embryonics inspired by fault-tolerant quantum computation.**[Citation Graph (0, 0)][DBLP] Conf. Computing Frontiers, 2005, pp:323-333 [Conf] - Lucian Prodan, Mihai Udrescu, Mircea Vladutiu
**A dependability perspective on emerging technologies.**[Citation Graph (0, 0)][DBLP] Conf. Computing Frontiers, 2006, pp:187-198 [Conf] - Mihai Udrescu, Lucian Prodan, Mircea Vladutiu
**Improving quantum circuit dependability with reconfigurable quantum gate arrays.**[Citation Graph (0, 0)][DBLP] Conf. Computing Frontiers, 2005, pp:133-144 [Conf] - Mihai Udrescu, Lucian Prodan, Mircea Vladutiu
**Implementing quantum genetic algorithms: a solution based on Grover's algorithm.**[Citation Graph (0, 0)][DBLP] Conf. Computing Frontiers, 2006, pp:71-82 [Conf] - Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo
**Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor.**[Citation Graph (0, 0)][DBLP] DDECS, 2007, pp:223-226 [Conf] - Lucian Prodan, Mihai Udrescu, Mircea Vladutiu
**Self-Repairing Embryonic Memory Arrays.**[Citation Graph (0, 0)][DBLP] Evolvable Hardware, 2004, pp:130-137 [Conf] - Lucian Prodan, Mihai Udrescu, Mircea Vladutiu
**Survivability of Embryonic Memories: Analysis and Design Principles.**[Citation Graph (0, 0)][DBLP] Evolvable Hardware, 2005, pp:280-289 [Conf] - Lucian Prodan, Mihai Udrescu, Mircea Vladutiu
**Multiple-level concatenated coding in embryonics: a dependability analysis.**[Citation Graph (0, 0)][DBLP] GECCO, 2005, pp:941-948 [Conf] - V. Muresan, Xiaojun Wang, Mircea Vladutiu
**A combined tree growing technique for block-test scheduling under power constraints.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2001, pp:255-258 [Conf] - Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
**A comparison of classical scheduling approaches in power-constrained block-test scheduling.**[Citation Graph (0, 0)][DBLP] ITC, 2000, pp:882-891 [Conf] - Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
**Power-Constrained Block-Test List Scheduling.**[Citation Graph (0, 0)][DBLP] IEEE International Workshop on Rapid System Prototyping, 2000, pp:182-187 [Conf] - Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
**Mixed Classical Scheduling Algorithms and Tree Growing Technique in Block-Test Scheduling under Power Constraints.**[Citation Graph (0, 0)][DBLP] IEEE International Workshop on Rapid System Prototyping, 2001, pp:162-167 [Conf] - Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
**The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints.**[Citation Graph (0, 0)][DBLP] VTS, 2000, pp:417-422 [Conf] - Cristian Ruican, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu
**Automatic Synthesis for Quantum Circuits Using Genetic Algorithms.**[Citation Graph (0, 0)][DBLP] ICANNGA (1), 2007, pp:174-183 [Conf] - Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai
**Simulated Fault Injection for Quantum Circuits Based on Simulator Commands.**[Citation Graph (0, 0)][DBLP] SACI, 2007, pp:245-250 [Conf] - Lucian Prodan, Mihai Udrescu, Oana Boncalo, Mircea Vladutiu
**Design for dependability in emerging technologies.**[Citation Graph (0, 0)][DBLP] JETC, 2007, v:3, n:2, pp:- [Journal] **Concurrent Error Detection for Multiplicative Inversion of Advanced Encryption Standard.**[Citation Graph (, )][DBLP]**Floating point multiplication rounding schemes for interval arithmetic.**[Citation Graph (, )][DBLP]**A high-speed AES architecture implementation.**[Citation Graph (, )][DBLP]**Round-level concurrent error detection applied to Advanced Encryption Standard.**[Citation Graph (, )][DBLP]**A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units.**[Citation Graph (, )][DBLP]**Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition.**[Citation Graph (, )][DBLP]**Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment.**[Citation Graph (, )][DBLP]**Quantum Circuit Synthesis with Adaptive Parameters Control.**[Citation Graph (, )][DBLP]**Performance Analysis for Genetic Quantum Circuit Synthesis.**[Citation Graph (, )][DBLP]**Fault-Tolerant Memory Design and Partitioning Issues in Embryonics.**[Citation Graph (, )][DBLP]**Discussing Redundancy Issues in Intelligent Agent-Based Non-traditional Grids.**[Citation Graph (, )][DBLP]**Built-in self test applicability for the non-linear operations of Advanced Encryption Standard.**[Citation Graph (, )][DBLP]**Genetic algorithm based quantum circuit synthesis with adaptive parameters control.**[Citation Graph (, )][DBLP]**Intrusions Detection in Intelligent Agent-Based Non-traditional Grids.**[Citation Graph (, )][DBLP]**Redundancy at Link Level for Non-Traditional Grids Implemented with Intelligent Agents.**[Citation Graph (, )][DBLP]
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