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Andy D. Pimentel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tessa E. Pronk, Simon Polstra, Andy D. Pimentel, Timo M. Breit
    Evaluating the Design of Biological Cells Using a Computer Workbench. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 2007, pp:88-98 [Conf]
  2. Cagkan Erbas, Selin C. Erbas, Andy D. Pimentel
    A multiobjective optimization model for exploring multiprocessor mappings of process networks. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:182-187 [Conf]
  3. Andy D. Pimentel, Cagkan Erbas
    An IDF-based trace transformation method for communication refinement. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:402-407 [Conf]
  4. Andy D. Pimentel, Louis O. Hertzberger
    Evaluation of LH*LH for a Multicomputer Architecture. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:217-228 [Conf]
  5. Andy D. Pimentel, J. van Brummen, T. Papathanassiadis, Peter M. A. Sloot, Louis O. Hertzberger
    Mermaid: modelling and evaluation research in MIMD architecture design. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1995, pp:335-340 [Conf]
  6. Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel
    TriMedia CPU64 Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:586-592 [Conf]
  7. Andy D. Pimentel, Louis O. Hertzberger
    An Architecture Workbench for Multicomputers. [Citation Graph (0, 0)][DBLP]
    IPPS, 1997, pp:94-99 [Conf]
  8. Cagkan Erbas, Selin C. Erbas, Andy D. Pimentel
    Static priority scheduling of event triggered real time embedded systems. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2004, pp:109-118 [Conf]
  9. Joseph E. Coffland, Andy D. Pimentel
    A Software Framework for Efficient System-level Performance Evaluation of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    SAC, 2003, pp:666-671 [Conf]
  10. Vinay Gupta, Mohit Modi, Andy D. Pimentel
    Performance evaluation of the LH*lh scalable, distributed data structure for a cluster of workstations. [Citation Graph (0, 0)][DBLP]
    SAC, 2001, pp:544-548 [Conf]
  11. Cagkan Erbas, Simon Polstra, Andy D. Pimentel
    IDF Models for Trace Transformations: A Case Study in Computational Refinement. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:178-190 [Conf]
  12. Andy D. Pimentel
    A Case for Visualization-Integrated System-Level Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:455-464 [Conf]
  13. Andy D. Pimentel, Simon Polstra, Frank Terpstra, A. W. van Halderen, Joseph E. Coffland, Louis O. Hertzberger
    Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:57-73 [Conf]
  14. Mark Thompson, Andy D. Pimentel
    A High-Level Programming Paradigm for SystemC. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:530-539 [Conf]
  15. Andy D. Pimentel, Louis O. Hertzberger, Paul Lieverse, Pieter van der Wolf, Ed F. Deprettere
    Exploring Embedded-Systems Architectures with Artemis. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2001, v:34, n:11, pp:57-63 [Journal]
  16. Peter M. A. Sloot, Andy D. Pimentel, Louis O. Hertzberger
    Design issues for high performance simulation. [Citation Graph (0, 0)][DBLP]
    Simul. Pr. Theory, 1998, v:6, n:3, pp:221-242 [Journal]
  17. Andy D. Pimentel, Cagkan Erbas, Simon Polstra
    A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:99-112 [Journal]
  18. Cagkan Erbas, Selin Cerav-Erbas, Andy D. Pimentel
    Multiobjective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 2006, v:10, n:3, pp:358-374 [Journal]
  19. Mark Thompson, Andy D. Pimentel
    Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:222-232 [Conf]
  20. Andy D. Pimentel, Mark Thompson, Simon Polstra, Cagkan Erbas
    On the Calibration of Abstract Performance Models for System-level Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:71-77 [Conf]
  21. Cagkan Erbas, Andy D. Pimentel, Selin Cerav-Erbas
    Static priority scheduling of event-triggered real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2007, v:30, n:1, pp:49- [Journal]
  22. Cagkan Erbas, Andy D. Pimentel, Selin Cerav-Erbas
    Static priority scheduling of event-triggered real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2007, v:30, n:1, pp:29-47 [Journal]
  23. Jarmo Takala, Timo D. Hämäläinen, Andy D. Pimentel, Stamatis Vassiliadis
    Editorial. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:8, pp:465- [Journal]
  24. Andy D. Pimentel, Stamatis Vassiliadis
    Editorial. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:43, n:2-3, pp:111- [Journal]

  25. A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs. [Citation Graph (, )][DBLP]


  26. Daedalus: toward composable multimedia MP-SoC design. [Citation Graph (, )][DBLP]


  27. Evaluation of runtime task mapping heuristics with rSesame - a case study. [Citation Graph (, )][DBLP]


  28. Signature-based Microprocessor Power Modeling for Rapid System-level Design Space Exploration. [Citation Graph (, )][DBLP]


  29. A Mixed-level Co-simulation Method for System-level Design Space Exploration. [Citation Graph (, )][DBLP]


  30. 2009 IEEE/ACM/IFIP 7th workshop on embedded systems for Real-Time multimedia (ESTIMedia 2009). [Citation Graph (, )][DBLP]


  31. System-level MP-SoC design space exploration using tree visualization. [Citation Graph (, )][DBLP]


  32. Introduction. [Citation Graph (, )][DBLP]


  33. System-level runtime mapping exploration of reconfigurable architectures. [Citation Graph (, )][DBLP]


  34. System-Level Design Space Exploration of Dynamic Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  35. Signature-Based Calibration of Analytical System-Level Performance Models. [Citation Graph (, )][DBLP]


  36. Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study. [Citation Graph (, )][DBLP]


  37. Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration. [Citation Graph (, )][DBLP]


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