The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Laurence V. Pierre: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem
    Formal Verification of VHDL Descriptions in the Prevail Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:2, pp:42-56 [Journal]
  2. Dominique Borrione, Amr Helmy, Laurence V. Pierre, Julien Schmaltz
    A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:127-136 [Conf]
  3. Dominique Borrione, Julia Dushina, Laurence V. Pierre
    A compositional model for the functional verification of high-level synthesis results. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:526-530 [Journal]

Search in 0.043secs, Finished in 0.043secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002