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Abdel Ejnioui: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Anuja Jayraj Thakkar, Abdel Ejnioui
    Pipelining of double precision floating point division and square root operations. [Citation Graph (0, 0)][DBLP]
    ACM Southeast Regional Conference, 2006, pp:488-493 [Conf]
  2. K. Sitaraman, N. Ranganathan, Abdel Ejnioui
    A VLSI Architecture for Object Recognition Using Tree Matching. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:325-334 [Conf]
  3. Abdel Ejnioui, Abdelhalim Alsharqawi
    Pipeline-Level Control of Self-Resetting Pipelines. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:342-349 [Conf]
  4. Abdel Ejnioui, Ronald F. DeMara
    Area Reclamation Strategies and Metrics for SRAM-Based Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:196-202 [Conf]
  5. Heng Tan, Ronald F. DeMara, Anuja Jayraj Thakkar, Abdel Ejnioui, Jason Sattler
    Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:253-256 [Conf]
  6. Abdel Ejnioui, N. Ranganathan
    Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:176-185 [Conf]
  7. Abdel Ejnioui, Abdelhalim Alsharqawi
    Self-resetting stage logic pipelines. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:174-177 [Conf]
  8. Abdel Ejnioui, N. Ranganathan
    Systolic algorithms for tree pattern matching. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:650-702 [Conf]
  9. Abdelhalim Alsharqawi, Abdel Ejnioui
    Synthesis of Self-Resetting Stage Logic Pipelines. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:260-262 [Conf]
  10. W. Kuang, J. S. Yuan, Abdel Ejnioui
    Supply Voltage Scalable System Design Using Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:161-166 [Conf]
  11. Abdel Ejnioui, Abdelhalim Alsharqawi
    Pipeline Design Based on Self-Resetting Stage Logic. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:254-257 [Conf]
  12. Abdel Ejnioui, Abdelkader Rhiati
    A Reconfigurable Memory Management Core for Java Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:309-312 [Conf]
  13. Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui
    Control and Data Flow Graph Extraction for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:192- [Conf]
  14. Rashad Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui
    Synthesis of Pipelined SRSL Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:71-76 [Conf]
  15. Abdel Ejnioui
    FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:437-438 [Conf]
  16. Abdelhalim Alsharqawi, Abdel Ejnioui
    Clockless Pipelining for Coarse Grain Datapaths. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:749-753 [Conf]
  17. Abdel Ejnioui, N. Ranganathan
    Design Partitioning on Single-Chip Emulation Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:234-239 [Conf]
  18. Abdel Ejnioui, N. Ranganathan
    Routing on Switch Matrix Multi-FPGA Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:248-253 [Conf]
  19. Vamsi Krishna, Abdel Ejnioui, N. Ranganathan
    A tree matching chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:280-285 [Conf]
  20. Ronald F. DeMara, Yili Tseng, Abdel Ejnioui
    Tiered Algorithm for Distributed Process Quiescence and Termination Detection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:11, pp:1529-1538 [Journal]
  21. Vamsi Krishna, N. Ranganathan, Abdel Ejnioui
    A tree-matching chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:277-280 [Journal]
  22. Abdel Ejnioui, N. Ranganathan
    A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:407-410 [Journal]
  23. Abdel Ejnioui, N. Ranganathan
    Routing on field-programmable switch matrices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:283-287 [Journal]
  24. Abdel Ejnioui, N. Ranganathan
    Multiterminal net routing for partial crossbar-based multi-FPGA systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:71-78 [Journal]

  25. Hardware Acceleration of the Generalized Finite Automata Algorithm. [Citation Graph (, )][DBLP]


  26. Prototyping of a Two-Phase Micropipeline on FPGAs. [Citation Graph (, )][DBLP]


  27. A Parallel Array to Accelerate GFA Modeling in Video Coding. [Citation Graph (, )][DBLP]


  28. Runtime Adaptation in Reconfigurable System-on-Chips. [Citation Graph (, )][DBLP]


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