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Shengchao Qin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shengchao Qin, Zongyan Qiu, Jifeng He
    Constructing Hardware/Software Interface Using Protocol Converters. [Citation Graph (0, 0)][DBLP]
    APAQS, 2001, pp:141-148 [Conf]
  2. Jifeng He, Zhiming Liu, Xiaoshan Li, Shengchao Qin
    A Relational Model for Object-Oriented Designs. [Citation Graph (0, 0)][DBLP]
    APLAS, 2004, pp:415-436 [Conf]
  3. Shengchao Qin, Jifeng He
    Partitioning Program into Hardware and Software. [Citation Graph (0, 0)][DBLP]
    APSEC, 2001, pp:309-316 [Conf]
  4. Shengchao Qin, Wei-Ngan Chin
    Mapping Statecharts to Verilog for Hardware/Software Co-specification. [Citation Graph (0, 0)][DBLP]
    FME, 2003, pp:282-300 [Conf]
  5. Shengchao Qin, Jin Song Dong, Wei-Ngan Chin
    A Semantic Foundation for TCOZ in Unifying Theories of Programming. [Citation Graph (0, 0)][DBLP]
    FME, 2003, pp:321-340 [Conf]
  6. Jin Song Dong, Ping Hao, Shengchao Qin, Jun Sun, Wang Yi
    Timed Patterns: TCOZ to Timed Automata. [Citation Graph (0, 0)][DBLP]
    ICFEM, 2004, pp:483-498 [Conf]
  7. Jin Song Dong, Ping Hao, Shengchao Qin, Xian Zhang
    The Semantics and Tool Support of OZTA. [Citation Graph (0, 0)][DBLP]
    ICFEM, 2005, pp:66-80 [Conf]
  8. Quan Long, Zongyan Qiu, Shengchao Qin
    The Equivalence of Statecharts. [Citation Graph (0, 0)][DBLP]
    ICFEM, 2003, pp:125-143 [Conf]
  9. Shengchao Qin, Jifeng He, Zongyan Qiu, Naixiao Zhang
    Hardware/Software Partitioning in Verilog. [Citation Graph (0, 0)][DBLP]
    ICFEM, 2002, pp:168-179 [Conf]
  10. Wei-Ngan Chin, Siau-Cheng Khoo, Shengchao Qin, Corneliu Popeea, Huu Hai Nguyen
    Verifying safety policies with size properties and alias controls. [Citation Graph (0, 0)][DBLP]
    ICSE, 2005, pp:186-195 [Conf]
  11. Jin Song Dong, Ping Hao, Xian Zhang, Shengchao Qin
    HighSpec: a tool for building and checking OZTA models. [Citation Graph (0, 0)][DBLP]
    ICSE, 2006, pp:775-778 [Conf]
  12. Viet-Anh Vu Tran, Shengchao Qin, Wei-Ngan Chin
    An Automatic Mapping from Statecharts to Verilog. [Citation Graph (0, 0)][DBLP]
    ICTAC, 2004, pp:187-203 [Conf]
  13. Jin Song Dong, Shengchao Qin, Jun Sun
    Generating MSCs from an Integrated Formal Specification Language. [Citation Graph (0, 0)][DBLP]
    IFM, 2004, pp:168-186 [Conf]
  14. Wei-Ngan Chin, Florin Craciun, Shengchao Qin, Martin C. Rinard
    Region inference for an object-oriented language. [Citation Graph (0, 0)][DBLP]
    PLDI, 2004, pp:243-254 [Conf]
  15. Wei-Ngan Chin, Huu Hai Nguyen, Shengchao Qin, Martin C. Rinard
    Memory Usage Verification for OO Programs. [Citation Graph (0, 0)][DBLP]
    SAS, 2005, pp:70-86 [Conf]
  16. Jifeng He, Shengchao Qin, Adnan Sherif
    Constructing Property-Oriented Models for Verification. [Citation Graph (0, 0)][DBLP]
    UTP, 2006, pp:85-100 [Conf]
  17. Huibiao Zhu, Shengchao Qin, Jifeng He, Jonathan P. Bowen
    Integrating Probability with Time and Shared-Variable Concurrency. [Citation Graph (0, 0)][DBLP]
    SEW, 2006, pp:179-189 [Conf]
  18. Shengchao Qin, Jifeng He, Zongyan Qiu, Naixiao Zhang
    An Algebraic Hardware/Software Partitioning Algorithm. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2002, v:17, n:3, pp:284-294 [Journal]
  19. Wei-Ngan Chin, Cristina David, Huu Hai Nguyen, Shengchao Qin
    Automated Verification of Shape, Size and Bag Properties. [Citation Graph (0, 0)][DBLP]
    ICECCS, 2007, pp:307-320 [Conf]
  20. Shengchao Qin, Guanhua He
    Linking Object-Z with Spec#. [Citation Graph (0, 0)][DBLP]
    ICECCS, 2007, pp:185-196 [Conf]
  21. Hai H. Wang, Shengchao Qin, Jun Sun, Jin Song Dong
    Realizing Live Sequence Charts in SystemVerilog. [Citation Graph (0, 0)][DBLP]
    TASE, 2007, pp:379-388 [Conf]

  22. A Heap Model for Java Bytecode to Support Separation Logic. [Citation Graph (, )][DBLP]


  23. Memory Usage Verification Using Hip/Sleek. [Citation Graph (, )][DBLP]


  24. An Interval-Based Inference of Variant Parametric Types. [Citation Graph (, )][DBLP]


  25. Multiple Pre/Post Specifications for Heap-Manipulating Methods. [Citation Graph (, )][DBLP]


  26. A Formal Soundness Proof of Region-Based Memory Management for Object-Oriented Paradigm. [Citation Graph (, )][DBLP]


  27. Analysing memory resource bounds for low-level programs. [Citation Graph (, )][DBLP]


  28. Enhancing modular OO verification with separation logic. [Citation Graph (, )][DBLP]


  29. Automated Verification of Shape and Size Properties Via Separation Logic. [Citation Graph (, )][DBLP]


  30. Verifying BPEL-Like Programs with Hoare Logic. [Citation Graph (, )][DBLP]


  31. Separation Logic for Multiple Inheritance. [Citation Graph (, )][DBLP]


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