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Publications of Author

1. Ulrich Brüning, Lambert Schaelicke
   ATOLL: A High-Performance Communication Device for Massively Parallel Systems. [Citation Graph (0, 0)][DBLP]
   APDC, 1997, pp:228-234 [Conf]
   
2. Lambert Schaelicke, Kyle Wheeler, Curt Freeland
   SPANIDS: a scalable network intrusion detection loadbalancer. [Citation Graph (0, 0)][DBLP]
   Conf. Computing Frontiers, 2005, pp:315-322 [Conf]
   
3. John B. Carter, Wilson C. Hsieh, Leigh Stoller, Mark R. Swanson, Lixin Zhang, Erik Brunvand, Al Davis, Chen-Chi Kuo, Ravindra Kuramkote, Michael Parker, Lambert Schaelicke, Terry Tateyama
   Impulse: Building a Smarter Memory Controller. [Citation Graph (0, 0)][DBLP]
   HPCA, 1999, pp:70-79 [Conf]
   
4. Branden J. Moore, Thomas Slabach, Lambert Schaelicke
   Profiling Interrupt Handler Performance through Kernel Instrumentation. [Citation Graph (0, 0)][DBLP]
   ICCD, 2003, pp:156-163 [Conf]
   
5. Timothy J. Dysart, Branden J. Moore, Lambert Schaelicke, Peter M. Kogge
   Cache implications of aggressively pipelined high performance microprocessors. [Citation Graph (0, 0)][DBLP]
   ISPASS, 2004, pp:123-132 [Conf]
   
6. John B. Carter, Wilson C. Hsieh, Mark R. Swanson, Lixin Zhang, Erik Brunvand, Al Davis, Chen-Chi Kuo, Ravindra Kuramkote, Michael Parker, Lambert Schaelicke, Leigh Stoller, Terry Tateyama
   Memory System Support for Irregular Applications. [Citation Graph (0, 0)][DBLP]
   LCR, 1998, pp:17-26 [Conf]
   
7. Lambert Schaelicke, Al Davis, Sally A. McKee
   Profiling I/O Interrupts in Modern Architectures. [Citation Graph (0, 0)][DBLP]
   MASCOTS, 2000, pp:115-123 [Conf]
   
8. Lambert Schaelicke, Al Davis
   Improving I/O Performance with a Conditional Store Buffer. [Citation Graph (0, 0)][DBLP]
   MICRO, 1998, pp:160-169 [Conf]
   
9. Lambert Schaelicke, Thomas Slabach, Branden J. Moore, Curt Freeland
   Characterizing the Performance of Network Intrusion Detection Sensors. [Citation Graph (0, 0)][DBLP]
   RAID, 2003, pp:155-172 [Conf]
   
10. Lambert Schaelicke, Michael Parker
    The design and utility of the ML-RSIM system simulator. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2006, v:52, n:5, pp:283-297 [Journal]
    
11. Lambert Schaelicke
    Evaluating the impact of the simulation environment on experimentation results. [Citation Graph (0, 0)][DBLP]
    Perform. Eval., 2005, v:61, n:4, pp:329-346 [Journal]
    
12. Lambert Schaelicke, Alan L. Davis
    Design Trade-Offs for User-Level I/O Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:8, pp:962-973 [Journal]
    
13. Lixin Zhang, Zhen Fang, Michael Parker, Binu K. Mathew, Lambert Schaelicke, John B. Carter, Wilson C. Hsieh, Sally A. McKee
    The Impulse Memory Controller. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:11, pp:1117-1132 [Journal]
    
14. 
    A Phase-Adaptive Approach to Increasing Cache Performance. [Citation Graph (, )][DBLP]
    
    
15. 
    Revisiting Cache Block Superloading. [Citation Graph (, )][DBLP]